From: David Instone (email@example.com)
Date: Thu Jan 27 2000 - 01:51:20 PST
So is there anything to be gained, or lost, by mounting the capacitor so
its 'plates' are perpendicular to the PCB instead of parallel to it.
That way each plate gets equal connection inductance.
(Also, if there is a difference, and the section is almost square how
do we tell which way its layered.)
Ray Anderson wrote:
> Our group has looked at this issue and performed some Ansoft Maxwell simulations
> on a typical ceramic capacitor structure. We found that as the capacitor
> structure becomes taller the current tends to crowd towards the bottom of
> the capacitor.
> So yes, your theory matches what we've seen.
> I'll check with the guy who made the measurements for an answer to
> your points 2 and 3.
> > I read a short article by Howard Johnson not too long ago that got me
> > thinking about the current density cross section in surface mount
> > capacitors. As we shrink the pc board layer thickness from component layer
> > to reference layer, the height dimension of the capacitor starts to look
> > very significant. I would expect that a .020" to .040" thick cap over a
> > 0.005 epoxy glass layer would show significant variation over it's vertical
> > profile, but I have no tools for modeling this.
> > So I have questions for this group:
> > - Has anyone ever tried to model this and am I totally out of my mind?
> > - Is the effect significant enough to warrant finding a shorter but wider
> > capacitor for a given value?
> > - Does the mutual inductance of the metalization layers in the capacitor
> > come into play, or can it be treated as a uniform dielectric block for
> > modeling.
> > This is probably all very silly and trivial, but I'm really interested in
> > the answer. Thanks!
> > Brent DeWitt
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