RE: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?

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From: Greim, Michael (mgreim@mc.com)
Date: Tue Mar 07 2000 - 07:09:18 PST


FYI,

        A six mil, 1.5 oz micro-strip trace separated from
        the adjacent plane by 4 mils will yield a characteristic
        impedance of roughly 53 ohms. So it is possible
        to get low impedances on surface microstrips. FYI.
        However, if you are targetting an 0.062 board thickness
        your plane separation will be large, lowering your
        inter-plane capacitance.

Best Regards,

Michael

> -----Original Message-----
> From: Fred Dehkordi [SMTP:FredD@texasmicro.com]
> Sent: Tuesday, March 07, 2000 9:43 AM
> To: 'si-list@silab.eng.sun.com'
> Subject: RE: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?
>
> Alex,
> I don't see that much of draw back. The only thing must be consider is the
> control impedance of these signals routed on outer layer. Those signal
> were
> routed in outer layer might get about 90 ohm control impedance and as far
> as
> I remember, PCI signals impedance match about 50-80 ohm. This is still
> possible by adding discrets to the circuitry and some smart engineering
> design.
> Just a reminder, routing SCSI signals on outer layers are a good move
> because these signals require about 100 ohm control impedance.
>
> Best Regards,
>
> Fred Dehkordi
> Design Engineer
> Radisys Corporation
> Communication Platforms Division
> Tel : (713) 541-8200 Ext # 244
> Email : fred.dehkordi@radisys.com
>
>
> > -----Original Message-----
> > From: Alex Li [SMTP:alexl@ati.com]
> > Sent: Monday, March 06, 2000 8:36 PM
> > To: 'si-list@silab.eng.sun.com'
> > Subject: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?
> >
> > Recently I saw a 4-layer mother board with 100 Mhz 128-bit memory bus.
> > This board has unusual signal-power-ground-signal stack up. I talked
> to
> > one of their engineer for this kind of arrangement. They said since
> most
> > PC motherboard has several power plane split and on the top level there
> > are a lot of components with pads. they think if they route all the
> > 128-bit memory bus on the back and put it close to ground plane, they
> have
> > much routing area and this will help to keep the signals clean.
> >
> > This is kind of new idea to me, does anyone see any drawback by
> this
> > arrangement ? Will this decrease the decoupling caps performance ?
> >
> > Alex
> >
> >
>
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