[SI-LIST] : on-chip decoupling capacitance (and SI)

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From: Sandy Taylor (cmos@rockisland.com)
Date: Tue Apr 18 2000 - 16:29:03 PDT


> I have heard rumors that modern microprocessors use 10s of nF of on-chip decoupling
> (presumably provided by large areas of thin oxide) to keep the core supply noise in a
> range where the flip-flops don't loose their minds.

Chris

For a solution running at 1GHz in a device drawing 80W in a 0.18u technology, look at:
"An On-Chip Voltage Regulator Using Switched Decoupling Capacitors" in ISSCC 2000.
I'll see if I can get a copy of the paper and slides for Ray to make available.

The on chip problems can be severe. 100s of nF is a reasonable for a large microprocessor today. This helps provide a reservoir of charge for the surge of current with each clock tick within a clock
cycle or for a step in the current due to an increase in activity over several cycles. With today's uP, the potential dI/dT is so severe that even using a flip chip ball grid array with hundreds of
power/ground pins and a carefully designed package you have no chance of seeing significant current from the board for several clock cycles.

Watch carefully for package resonance. This can occur way below the clock frequency. The on chip capacitors should be constructed as devices using gate oxide as you mentioned, but keep the channel length
long to INCREASE THE SERIES RESISTANCE to provide optimum damping over the multi-cycle resonance. Strangely enough, almost everything that was done to "improve" CMOS technology has helped build a better
resonant tank circuit (not good for CMOS).

> Does anyone know of a similar email reflector that deals with chip design issues
> such as this, or are we SI guys the only ones lucky enough to have a Ray
> Anderson to set something like this up?

Simplex Solutions has software for extraction and analysis.
They have papers about on-chip SI issues including clock and power:
http://www.simplex.com/udsm/reference.html

Sandy Taylor

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