[SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs

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From: Netzler Dirk (Dirk.Netzler@icn.siemens.de)
Date: Thu Feb 10 2000 - 23:01:47 PST


Hello All,

every time I have to design memory buses I wonder wether signals at adress
inputs
of synchronous memory chips (SDRAM, SSRAM) ) must have monotonic edges or
not.
If yes, can anybody give me an explanation for that ?

And what's about FEPROMs ? Okay, the control signals (e.g. WE,OE) need to be
monotonic.
But what's about the adress inputs ? Should they be monotonic, too ? I don't
find reasons for that.

What are your experiences ?

Best regards

Dirk Netzler
Siemens AG

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