From: Tom Zimmerman (email@example.com)
Date: Wed Feb 02 2000 - 08:57:27 PST
Thanks, D.C., for the comments. A few more questions...
> > 1. My basic understanding of LVDS (which may be incorrect) is that a
> > constant current of several mA is supplied to one of the output pads
> > are terminated in approx. 100 ohms) in order to supply a voltage
> > differential across the load of several hundred mv. In order to
> > common mode voltage (approx. 1.2 V), the other pad must effectively be
> > connected to a voltage source. Is this really the way LVDS is done?
> No. LVDS requires that the difference between Vos (output common mode)
> Vod (output differential) for one and zero be kept pretty small. In other
> words, signaling must be balanced.
National shows in their "Introduction to LVDS" essentially a current source
and a voltage source which the 2 output pads are switched to, in one
polarity or the other depending on the state of the input. I'm wondering
why they show this if this is not the way it's done! How is the balanced
drive achieved? Are there 2 equal valued current sources, and if so, how is
the common mode voltage established? Or are there 2 voltage sources with 50
ohm impedance? What's the output impedance of an LVDS driver anyway, 50
ohms per output pad or infinite?
> CML has the extremely nice properties of
> 1) really, really, low differential skew (it's easy to balance the drive)
> 2) simple receiver (the common-mode issue is easy for current drive)
> and the truly ugly property of
> 3) hideous power dissipation.
Sorry, I guess I still am not sure exactly what CML is -- is it indeed
basically just a differential pair with constant current bias and open
collectors or drains which switches the current to one output pad or the
other? If so, then why is the power dissipation so hideous (compared to
PECL or LVDS)? According to your comments, it sounds like if you can afford
the power dissipation, it's a nice way to go. (I only have to drive a few
bits worth of digital information off-chip).
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