From: Yu Wang (firstname.lastname@example.org)
Date: Wed Apr 05 2000 - 21:09:46 PDT
I'm not sure if it will be helpful to your case.
whatever you can try. I heard about a delay reset chip
from TI or Maxim(should be one of them, I can check it
later). It generates a delayed reset pulse(the delay
is a big amount of time) after power on.
--- Andy Peters <email@example.com> wrote:
> Thanks to all who've responded. Here's what I
> intend to do. I found a TI
> part (CDCF2509) with built-in source terminations
> and nine outputs. The
> oscillator will feed the reference input. The five
> "1Y" outputs will feed
> an FPGA and its four SDRAMs (two of the SDRAMs are
> on top of the board, the
> other two are on the bottom). One of the "2Y"
> outputs will feed a third
> FPGA's clock input. A second "2Y" output will feed
> a second CDCF2509. The
> five "1Y" outputs of the second PLL buffer will feed
> the second FPGA and its
> four SDRAMs. The "2Y" outputs of the second PLL
> buffer will be disabled.
> The board has a clocks-only layer, so we don't think
> we'll have too much
> trouble trying to keep the clock line lengths all
> The only "gotcha" here is that the VME interface
> control chip, a Cypress
> (@#$%!) part, requires an 80 MHz clock, but that
> part has a built-in
> power-on reset circuit that enables it to configure
> itself. That
> configuration fails if the clock is not running, and
> the ~1 ms PLL buffer
> startup time is too long. It seems as if the only
> solution is to run two
> traces from the oscillator - one to the first buffer
> and the second to the
> VME chip. I don't think it's a problem keeping
> those traces equally short,
> and the oscillator data sheet says it can drive +/-
> Again, much thanks to the gurus.
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> 520 318 8191
> "Money is property; it is not speech."
> -- Justice John Paul Stevens
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Yu Wang, Ph.D
U.T. MD Anderson Cancer Center
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Houston, TX, 77030
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