[SI-LIST] : Program: Workshop on SIGNAL PROPAGATION ON INTERCONNECTS

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From: Treytnar Dieter (dieter@lfi.uni-hannover.de)
Date: Thu Mar 16 2000 - 01:34:04 PST


                                PROGRAM

                         4th IEEE WORKSHOP ON

                 SIGNAL PROPAGATION ON INTERCONNECTS
          Sponsorship in cooperation with the German section
                     of the IEEE Computer Society

                             May 17-19, 2000
                 Parkhotel Herrenkrug, Magdeburg, Germany

                   http://www.tet.uni-hannover.de/SPI

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As a result of the success of the 3rd Workshop on Signal Propagation on
Interconnects we will continue this meeting with the "4th International
Workshop on Signal Propagation on Interconnects" to be held in Magdeburg in
cooperation with the IEEE Computer Society and sponsored by the German
Computer Chapter. It is the intent of this workshop to report on recent
developments and approaches in the field of interconnect simulation and
measurement on chips as well as on boards and packages.
The workshop will be held in English. The committee looks forward to your
participation.

Current and up-to-date information about the workshop can be found on the
website http://www.tet.uni-hannover.de/SPI.

The topics of the workshop are:

Modeling
Numerical Methods
Simulation
Measurement Techniques
Radiation and Interference
Transmission Line Theory
System Design Issues

Program
 TUESDAY, MAY 16
 Early Registration 6:00 PM - 8:00 PM
 Welcome Reception and Buffet 6:00 PM - 9:00 PM

 WEDNESDAY, MAY 17
 Registration 8:00 AM - 5:00 PM

 Opening Session

09:00 Welcome Address
J.P. Mucha, Univ. Hannover, GERMANY

 Session 1: Modeling I

09:10 Passive Model-Reduction of Distributed Transmission Line Networks
Using Exponential Padé Based Macromodels
A. Dounavis, E. Gad, R. Achar, M. Nakhla, Carleton Univ., Ottawa, CANADA

09:40 Behavioral Modeling of Digital Devices via Black-Box Identification
F.G. Canavero, I.A. Maio, I.S. Stievano, Politecnico di Torino, ITALY

10:10 Analytical Models for Inter- and Intra-Layer Capacitance Extraction in
a 0.25 µm CMOS Technology
D. Bernard, C. Landrault, P. Nouet, LIRMM, Université Montpellier II, FRANCE
10:40 Coffee Break

 Session 2: Numerical Methods

11:10 Flip-Chip Package Interconnect Modeling Using FDTD
D. Lambalot, S. Chen, J.E. Schutt-Ainé, Univ. of Illinois, Urbana, USA

11:40 Field Analysis in Stripline Circuits
S. Kabir, S.L. Dvorak, J.L. Prince, Univ. of Arizona, Tucson, USA

12:30 Lunchbuffet

 Session 3: Radiation and Interference

14:00 Symmetrical Retarded Current Source Model for Transient Field Coupling
on Interconnects
M. Kurten1, U. Keller1, W. John1, K. Meerkoetter2, H. Reichl1, 1FhG-IZM,
Berlin/Paderborn, 2Univ.-GH Paderborn, GERMANY

14:30 Near and Far Field Measurement from IC and Surrounding on PCB
N. Schibuya, T. Takahashi, T. Sakusabe, Takushoku Univ., Tokyo, JAPAN

15:00 Calculation of Signal Interferences to Electronic Systems Caused by
Electromagnetic Irradiation
J. Bohl, T. Ehlen, F. Sonnemann, DIEHL Munitionssysteme GmbH & Co.,
Roethenbach, GERMANY

15:30 Radiation and Interference Issues in Practical Dielectric
Interconnects and Interfaces
W.J. Sarjeant1, I. Kohlberg1, G. Blaise2, 1School of Engineering and Applied
Science, Buffalo, USA, 2Université Paris-Sud, FRANCE

16:00 Coffee Break

 Session 4: Measurement Techniques I

16:30 Broadband Measurement of Asymmetric Coupled Lines Built in a 0.25 µm
CMOS Process
U. Arz1, D.F. Williams2, D.K. Walker2, J.E. Rogers2, M. Rudack1, D.
Treytnar1, H. Grabinski1, 1Univ. Hannover, GERMANY, 2NIST, Boulder, USA

17:00 Characterization of Propagation and Crosstalk Effects on Long Lossy
Interconnects of High Speed VLSI Circuits
C. Bermond1, B. Fléchet1, G. Le Carval2, F. Charlet2, Y. Morand3, G.
Angénieux1, 1LAHC, Univ. de Savoie, Le Bourget du Lac, 2LETI, Grenoble, 3ST
Microelectronics, Grenoble, FRANCE

 TUESDAY, MAY 18
 Registration 8:00 AM - 4:00 PM

 Session 5: Modeling II

09:00 Calculation of Ground-Noise On-Chip Level for Short-Channel
Transistors
M. Faferko2, W. John1, H. Reichl1, 1FhG-IZM, Berlin/Paderborn, 2Univ.-GH
Paderborn, GERMANY

09:30 Development of CAD-Oriented Models for On-Chip Interconnects on
Silicon
J. Zheng, V.K. Tripathi, A. Weisshaar, Oregon State University, Corvallis,
USA

10:00 Coffee Break

 Session 6: Simulation

10:30 Time-Domain Far-End Crosstalk Waveforms in Multiconductor Microstrip
Line with Covering Dielectric Layer
T.R. Gazizov, S.V. Poluektov, Tomsk State University of Control Systems and
Radioelectronics., Tomsk, RUSSIA

11:00 Accurate and Efficient Transient Simulation of Interconnect Networks
with Nonlinear Terminations
S. Grivet-Talocia, F.G. Canavero, Politecnico di Torino, ITALY

12:30 Lunchbuffet

 Session 7: System Design Issues I

14:00 Measurements of Signal Transmissions Using a Source Synchronous
Wave-Pipeline Interface across Multiple Interface Structures
M.F. McAllister, H. Harrer, J. Chen, IBM, Poughkeepsie, USA

14:30 Power Density Spectrum for Line Codes based on Pseudo Random Binary
Sequences
A. Knobloch, H. Garbe, Univ. Hannover, GERMANY

15:00 Coffee Break

 Session 8: Measurement Techniques I

15:30 Comparison of TDR and Network Analyzer Measurements for Extracting
S-Parameter Data
S. Pannala, M. Swaminathan, School of Electrical and Computer Eng., Georgia
Institute of Technology, Atlanta, USA

16:00 Impedance Measurement in Time and Frequency Domain
K. Helmreich, A. Lechner, Advantest (Europe) GmbH, Munich, GERMANY

18:30 Social Event: Enjoy the magic of the historical ambience of an old inn
with a medieval seven-part menue. We also welcome you to attend the original
experiment of the famous german physicist Otto von Guericke (1602-1686).

 FRIDAY, MAY 19

 Session 9: Transmission Line Theory

09:00 Circuital Representation of Nonuniform Transmission Lines
A. Maffucci, G. Miano, Univ. di Napoli, ITALY

09:30 Theoretical Analysis of Signal Reflections on Cu On-Chip
Interconnections
D. Deschacht1, F. Huret2, G. Servel1, E. Paleczny2, P. Kennis2, 1U.M.R.
C.N.R.S., Montpellier, 2U.M.R. C.N.R.S., Villeneuve d´Ascq, FRANCE

10:00 Time-Delayed Chua's Circuit with Lossy Transmission Line
L.A. Corti, Univ. di Napoli, ITALY

10:30 Coffee Break

 Session 10: System Design Issues II

11:00 Determination of Critical Line Length for On-Chip Interconnects for
the Future Technologies as Predicted in the SIA Roadmap
T.-M. Winkel, D. Kaller, A. Huber, IBM Deutschland, Boeblingen, GERMANY

11:30 Crosstalk Compensation in Iinterconnections for High Speed
Applications
F. Ndagijimana, LEMO-UMR, Grenoble, FRANCE

12:00 Discussion and Summary
J.P. Mucha, Univ. Hannover, GERMANY

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WORKSHOP FEES

 Registration before April 15 Registration after April 15
IEEE Member DM 560 DM 610
Non-member DM 690 DM 780

The registration fee includes: meals, workshop registration package,
refreshments, and social event. This is an unbreakable package.

ACCOMMODATION

Hotel reservations must be made directly with:

Parkhotel Herrenkrug
"IEEE Workshop"
Herrenkrug 3
D-39114 Magdeburg
Tel.: +49-391 8508-0
Fax: +49-391 8508-501

There are special room rates for workshop attendees. Please make sure to
mention that you are attending the IEEE Workshop.

Single Room/day: DM 166
Double Room/day: DM 236

A full breakfast menu is included in the room rates.

Since the number of rooms is limited in both categories reservations should
be made as soon as possible (before April 15) and can only be accepted on a
space available basis.

TRANSPORTATION

Magdeburg is located between Hannover and Berlin.
There are direct InterCity (IC), InterRegio (IR) or RegionalExpress (RE)
train connections from Hannover (IC, IR) as well as from Berlin (IR, RE)
every hour (1½ hours driving time) to Magdeburg.

The Hotel Herrenkrug can be reached via taxi or via tram (line #6, direction
»Herrenkrug«, till terminal station).

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 General Chair:
Joachim P. Mucha
University of Hannover
Institut fuer Theoretische Elektrotechnik
Appelstr. 9A
D-30167 Hannover
Tel: +49 511 762 3201/3202
Fax: +49 511 762 3204
mucha@tet.uni-hannover.de

Vice Chair:
Thomas W. Williams
Synopsys, Inc.
1113 Spruce Street
Boulder, CO 80302
Tel: +1 303 245 0493
Fax: +1 303 938 5005
tww@synopsys.com

 Program Chair:
Hartmut Grabinski
University of Hannover
Laboratorium fuer Informationstechnologie
Schneiderberg 32
D-30167 Hannover
Tel: +49 511 762 5030/5043
Fax: +49 511 762 5051
hgra@lfi.uni-hannover.de

Co-Chair:
Petra Nordholz
Infineon Technologies AG
MP PTS
D-81730 Muenchen
Tel: +49 89 234-49207
Fax: +49 89 234-719903
petra.nordholz@infineon.com

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Technical Program Committee:

W. Bandurski, Univ. Poznan (PL)
F. Canavero, Univ. Torino (I)
D. De Zutter, Univ. Ghent (B)
H. Dirks, Univ. Kiel (D)
H.-J. John, SNI, Paderborn (D)
W. John, FhG-IZM, Paderborn (D)
E. Kuh, Univ. Berkeley (USA)
N. van der Meijs, Univ. Delft (NL)
J.P. Mucha, Univ. Hannover (D)
M. Nakhla, Carleton University (CAN)
P. Nordholz, Infineon Technologies (D)
O.A. Palusinski, Univ. of Arizona (USA)
H.J. Pfleiderer, Univ. Ulm (D)
L.T. Pileggi, Carnegie Mellon (USA)
J.L. Prince, Univ. of Arizona (USA)
K. Reiss, Univ. Karlsruhe (D)
A. Rubio, Univ. UPC Barcelona (E)
A.E. Ruehli, IBM, Yorktown Heights (USA)
J. Schutt-Ainé, Univ. Illinois (USA)
E. Sicard, INSA, Toulouse (F)
A. Simsek, FhG-IZM, Berlin (D)
R. Velazco, TIMA, Grenoble (F)
D.F. Williams, NIST, Boulder (USA)
T.W. Williams, Synopsys, Boulder (USA)
Y. Zorian, LogicVision, San Jose (USA)

==================================================
Dipl.-Ing. Dieter Treytnar
Laboratorium fuer Informationstechnologie
Schneiderberg 32 D-30167 Hannover, Germany
Tel. +49-511-762-5031 Fax +49-511-762-5051
E-Mail: dieter@lfi.uni-hannover.de dtre@gmx.de
http://www.tet.uni-hannover.de/~dtre
==================================================

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