Re: [SI-LIST] : Stack up

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From: sweir (weirsp@a.crl.com)
Date: Mon Feb 21 2000 - 17:09:13 PST


Iulian,

If you need Sig5 for LVDS, get the PECL clocks out of Sig6. Also, do you
have a substantial number or single-ended signals? If so, you need to take
proper care to avoid crosstalk between those and the LVDS signals as well.

Will the PECL clocks fit on signal bottom? If so, then I suggest the
following as a symmetric stack-up that will reduce your crosstalk problems
between the PECL clocks and LVDS:

Signal top
1.8
Gnd
S1
S2
Gnd
S3
S4
Gnd
S5
S6
Gnd
3v3
Signal Bottom -Pecl clocks

Regards,

Steve.
At 11:23 AM 2/21/00 -0800, you wrote:

>Hi
>
>I'm listening to this list for some time now and I would like to ask your
>opinion on a stack-up I'm working on.
> It is a board with 4x64 pairs of LVDS signals, 77.76 MHz clock, high
>speed(777.6 Hb/s).
>
> I came up with a 14 layers that looks like that:
>
>Signal top fanout, some analog power
>1.8V
>Gnd
>Sig1 LVDS
>Sig2 LVDS
>Gnd
>Sig3 LVDS
>Sig4 LVDS
>Gnd
>Sig5 LVDS
>Sig6 PECL clocks
>3.3V
>Gnd
>Signal bottom fanout
>
> I'll be using 1.6 mil core for my high speed cap.
> I would gladly use less layers, but I'm being forced by the HS3
>connectors.
>
> I would really appreciate your opinion.
>
>
>
>Thanks,
>
>Iulian Ungureanu
>PCB Designer
>PMC-Sierra,Inc.
>Iulian_Ungureanu@pmc-sierra.com
>http://www.pmc-sierra.com
>Voice:(604)415-6053 Ext.2586
>Fax:(604)415-6206
>
>
>
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