From: Brent DeWitt (firstname.lastname@example.org)
Date: Tue Apr 04 2000 - 20:24:00 PDT
First, I'm not an SI guru, but I have been primarily involved with EMC for
25 years. Take my opinion with a large block of salt! My first impression
is that this is the last thing in the world you want to do (no offense
meant). You seem to be applying signal crosstalk methods to the power
distribution. If we assume that you cannot keep current off of the routed
PWR traces, then you would want to give them the best coupling back to
reference that you can. I'm sure lot's of more qualified folks will chirp
in, but my thought is that you want _maximum_ coupling between your power
and ground planes, not minimum.
> -----Original Message-----
> From: email@example.com
> [mailto:firstname.lastname@example.org]On Behalf Of Ilya Zaverukha
> Sent: Tuesday, April 04, 2000 8:01 PM
> To: email@example.com
> Subject: [SI-LIST] : PWR/GND grid effect on EMI
> Hello SI experts,
> I'm relaying out a pcb for one of my customers. The goal is to
> reduce the cost
> by going from 4-layer (internal PWR and GND planes) bd. down to
> 2-layers. One
> of the major concerns is increased EMI.
> One of the ideas that was brought up to minimize EMI is to have a
> "grid" of
> horizontal PWR traces spaced around 2cm from each other on top side and
> vertical GND traces spaced 2cm on the opposite side. In addition,
> the board
> would have a GND ring around the perimeter on both sides that
> would be stiched
> with vias. Every point of intersection of these PWR and GND lines
> will have a
> .01uF and .1uF bypass cap.
> Since I haven't heard about this approach, your input would be
> --Ilya Z.
> IZ Circuits
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