RE: [SI-LIST] : trace width for clock routing- wider/narrower?

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From: 林朝煌 (John@quantatw.com)
Date: Mon Mar 13 2000 - 17:00:21 PST


Hi Shannon,
 
Thank you for shedding light.
 
I agree with you about PCB trace variation due to allowable tolerance.
Thank you for reminding.
 
You are right that wider traces will have lower skin effect losses as well
as
DC loss. However, wider trace also increase loss due to dielectric layer.
 
With RLGC model for Lossy transmission line, wider trace decrease R_dc,
R_skin loss, however, increase G loss and C loss.
 
The increasing G loss and C loss may be help in decreasing EMI radiation
because of attenuating high frequency components in a waveform of signal.
 
The decreasing R_dc and R_skin may be help in maintaining the amplitude of
the signal.
 
This makes me think of Rambus ...
 
Best Regards,
 

John Lin
SI Engineer
Quanta Computer Inc.,Taiwan, R.O.C.
Email: John@quantatw.com <mailto:John@quantatw.com>
Tel: 886+3+3979000 ext. 5183

 

-----Original Message-----
From: Shannon Roseman [mailto:shannon@compatible.com]
Sent: Monday, March 13, 2000 12:44 PM
To: John@quantatw.com
Subject: Re: [SI-LIST] : trace width for clock routing- wider/narrower?

Hi John,
If you want to hold really tight tolerance, you may want to consider the
tolerance on trace width for the PCB. If you have a 5 mil trace with +/- 1
mil tolerance, you might get a 10 to 20% variance in the impedance. With a
10 mil trace with +/- 1 mil tolerance, the variation on impedance should be
twice as good(5 to 10%).
 
Wider traces also give lower losses at higher frequencies. We had to go with
17 mil wide traces on some 1GHz 18inch long traces to deliver the proper
voltage swing at our receivers. Narrower traces attenuated the signals
enough to make the signal too small at the receiver.
 
I think the short answer is to make the traces as narrow as possible (to
conserve board routing resources) and still satisfy all the other design
requirements. The right answer is usually a compromise of all the design
requirements.
 
Shannon Roseman
Senior Hardware Engineer
Compatible Systems

-----Original Message-----
From: John Lin (aL!|A!P!N) <>
To: si-list@silab.eng.sun.com <mailto:si-list@silab.eng.sun.com> <
si-list@silab.eng.sun.com <mailto:si-list@silab.eng.sun.com> >
Date: Sunday, March 12, 2000 6:17 PM
Subject: [SI-LIST] : trace width for clock routing- wider/narrower?

Dear All SI experts,

For clock routing, does wider trace width have more advantage than narrower
one ,in term of better electrical properties, under the condition of same
trace to space ratio and good match in impedance with source terminators?

For example, 5 mils trace width with 10 mils trace spacing versus 10mils
trace width with 20 mils trace spacing.

Thank you for your helps in advance.

John Lin
SI Engineer
Quanta Computer Inc.,Taiwan, R.O.C.
Email: John@quantatw.com
Tel: 886+3+3979000 ext. 5183

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