From: Ritchey Lee ([email protected])
Date: Fri Mar 03 2000 - 16:46:15 PST
The problem with this technique is that modern ICs need decoupling capacitance at frequencies much higher than the bulk capacitors or any discrete capacitors can provide. That capacitance comes from the
power plane structure. If you cut up you planes as you suggest, this will not be the case. Plane cuttnig is a bad idea. It produces more noise than it ever eliminates. Many EMI problems I fix are f
rom the cutting of planes.
In addition, wouldn't it be good to establish that there is some real noise problem before setting off to break up planes, add parts and increase product cost?
Keith Amundsen wrote:
> We have been looking at creative power plane connections. For subsystems on
> a board (of one or more chips) we are considering isolating the power plane
> under each of them. This would be done with a narrow moat between the
> rectangular island and the rest of the power plane. The moat would be
> bridged with ferrites. The island would have a bulk storage (10 or 33uF)
> for each ferrite and a number of bypass (multiple values) capacitors for
> each chip. These would be connected to the solid ground plane. Their are
> many pros and cons to doing this and we thought a wider audience might help.
> -----Original Message-----
> Subject: RE: [SI-LIST] : Adding inductors to ground?
> **** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:18 PDT