From: D. C. Sessions (email@example.com)
Date: Fri Apr 07 2000 - 16:56:13 PDT
> We are using some 484 pin BGA's (FPGA's), which have edge rates of about 170ps.
> Using a series termination, it would have to be placed within 1/10 of the
> transition length according to Howard Johnson. On FR4, the transition length
> would be .98, making the distance from source to termination .098. It is not
> possible to get all of the required termination's within that distance.
> Aside from slowing down the edges (not desirable), waiting longer for things to
> settle, or going with buried resistance, are there any other solutions for
> placement of termination's? How are other people terminating large, high pin
> count devices?
I'm prejudiced: I design the I/Os to match line impedance, neener neener.
If that doesn't work, then you may be able to get remarkably good results
by putting a single resistor in the middle of the line. This approach
works best when the drivers at each end are nearly matched anyway, but it
works surprisingly well even when they're quite a bit too strong.
For small groups of signals with really critical performance, we sometimes
double up the I/Os: we run the same signal in, over to the adjacent diepad,
and out again to the terminator. No stubs.
-- D. C. Sessions firstname.lastname@example.org
**** To unsubscribe from si-list or si-list-digest: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:06 PDT