RE: [SI-LIST] : Decoupling strategy on 622MHz devices

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From: Chris Cheng (chris.cheng@3pardata.com)
Date: Thu Apr 06 2000 - 11:41:18 PDT


with 400ps edges, the only way you can remotely have a
chance to decouple the i/o is using flip chips and have
LICC or LICA caps on top of the package. any other place
will be electrically too far from the i/o pad.
chris

-----Original Message-----
From: Steeve Gaudreault [mailto:sgaud@nortelnetworks.com]
Sent: Thursday, April 06, 2000 10:19 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Decoupling strategy on 622MHz devices

Hi,

I need a breakout strategy for the ASICs (BGA 383pins)
that we have on the board. They all have lot 622MHz I/F.
Those ASICs have a separate VDBB for those 622MHz I/Os.
We put decoupling caps inside the device close to the die,
but we also need a strategy for the decoupling on the board.
At those frequencies/rise time (BTW rise time = 400ps), the
effect of the parasitic becomes important when we do our
decoupling strategy. I'd like to get some advice as for having
decoupling between the ASIC and the board versus having the
decoupling on the secondary side. I no for sure that manufacture
won't like the first option but I'd like to get advises from the
experts before I choose which way to go.

thanks,

Steeve Gaudreault
H/W Engineer, Nortel Networks
* sgaud@nortelnetworks.com <mailto:sgaud@nortelnetworks.com>

        -----Original Message-----
        From: Chris Bobek [SMTP:cbobek@cadence.com]
        Sent: Wednesday, January 26, 2000 2:43 PM
        To: si-list@silab.eng.sun.com
        Subject: Re: [SI-LIST] : Decoupling capacitor resonance

        Hi,

        Thank you for all of your responses. So, are most of you saying
that in my case, the 0.1uF is probably ok and to not bother purchasing
10pF
caps for this
        application?

        Something I realized is that when this appnote tells you what caps
to use for decoupling, they don't specify a package. So, they might say
"use a 22uF and
        a 10pF", but they could be using through hole versions, while I'm
using small SMT versions. My resonance will be entirely different from
theirs (also
        because of layout differences). The same would be true if they were
using 1206 and I'm using 0805.

        The bottom line for me is that the PLL is working great on our
prototype with the 22uF and 0.1uF. We have 4 ground planes and there
aren't
any other
        signals around the PLL. I seriously doubt it's worth the trouble
and complication of adding a brand new part to the BOM just to satisfy
an
appnote that
        happens to use different values.

        Thanks for all of your help, it will come in handy in the future,

        Chris

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