From: D. C. Sessions (firstname.lastname@example.org)
Date: Mon Feb 14 2000 - 09:42:21 PST
Netzler Dirk wrote:
> Hello All,
> every time I have to design memory buses I wonder wether signals at adress inputs
> of synchronous memory chips (SDRAM, SSRAM) ) must have monotonic edges or not.
> If yes, can anybody give me an explanation for that ?
SDRAM inputs (clocks excepted, of course) aren't the usual simple
buffer. For speed/power reasons, they are typically quite similar
in design to sense amps. DRAM manufacturers are reluctant to
discuss circuit details, but from behavior it's pretty clear that
they use dynamic logic -- the inputs are only sampled immediately
at clock edges.
Obviously, nonmonotonicity during the setup/hole window will result
in unpredictable behavior. Funny stuff *outside* of that window will
have little or no effect.
-- D. C. Sessions email@example.com
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