**From:** Ron Miller (*[email protected]*)

**Date:** Fri Mar 17 2000 - 11:13:44 PST

**Next message:**Ron Miller: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Previous message:**Mayer, Mike: "RE: [SI-LIST] : Fast edges with limited plane capacitance"**In reply to:**Larry Smith: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Next in thread:**S. Weir: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**S. Weir: "Re: [SI-LIST] : Fast edges with limited plane capacitance"

Larry

I have some issues as follows

*>
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*> So, if we compare the two power plane pairs below with 4 and 40 mil
*

*> separations:
*

*>
*

*> The velocities are constant.
*

*>
*

*> The capacitance of the 4 mil planes is 10X the 40 mil plane.
*

Capacitance as you mentioned above is proportional to the inverse of the

square of the distance making 4 mils 100 X the 40 mil plane.

*>
*

*>
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*> The inductance of the 40 mil plane is 10X the 4 mil plane.
*

The inductance does not change with dielectric thickness. In fact if you

look at a smith chart you will note that the low impedance outside circles

tend to approximate the outer circle as you go out. The outside circle

follows the electrical length and cannot be made larger then the length

of the line. This is a limit.

*>
*

*>
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*> The impedance of the 40 mil plane is 10X the 4 mil plane.
*

The impedance normally used for traces proportional to W/H might

be used as a basis for comparing low frequency signals, and therefore

this would hold. However, for a wide plane, and a high frequency

signal, the capacitance a quarter wavelength out has no effect and so

also the impedance effect. As the width approaches the quarter wavelength

of the frequency under consideration the impedance decreases at a

squared rate of the proportion of width to quarter wavelength with the

capacitance.

*>
*

*>
*

*> To directly answer Mark's questions, with the same amount of noise
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*> stimulation, there will be much more noise between the 40 mil power
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*> planes than between the 4 mil planes, in fact 10X. The reason is
*

*> because of the increased impedance.
*

Total capacitance will be 100 times

Xc will be 1/100

Since P=E*2/Z, P being constant

E=Sqrt(P/Z) substitute Xc for Z

E=Sqrt(1/Z) = 1/10

Yes the apparent noise voltage for 4 mils is 1/10 the voltage at 40 mils.

*>
*

*>
*

*> It turns out that one of the most important consequences of thin power
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*> planes is the 10X decrease in inductance. This greatly increases the
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*> effectiveness of the discrete decoupling capacitors that are mounted on
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*> the power planes.
*

Cant buy this.

*>
*

*>
*

*> I vote for the s-s-G-P-s-s stackup. Not only does it have better
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*> capacitance properties, but it also has better inductance and impedance
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*> properties. SI and EMI noise are greatly reduced. Microstrip
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*> transmission lines work just fine.
*

For minimum crosstalk, ground bounce and supply sag this is the best because the G-P layers can be made thinner as noted.

However, for minimum EMI, sandwiching the traces internally between

the power/ground planes may be preferrable.

Sorry we do not agree.

Ron Miller

*>
*

*>
*

*> regards,
*

*> Larry Smith,
*

*> Sun Microsystems
*

*>
*

*> > Date: Fri, 17 Mar 2000 10:29:33 -0600 (CST)
*

*> > From: mjs <[email protected]>
*

*> > To: "'[email protected]'" <[email protected]>
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*> > Subject: [SI-LIST] : Fast edges with limited plane capacitance
*

*> > MIME-Version: 1.0
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*> >
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*> >
*

*> > Let's assume that a power subsystem has a low, flat impedance up to a few
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*> > hundred MHz, and has a pair of realtivly unbroken planes. Only problem is
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*> > that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
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*> > will be a problem unless all noisy digital signals are 'sandwiched'
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*> > between the planes. This board also has parts with 1-2ns edge rates.
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*> >
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*> > I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
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*> > allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
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*> > yielding much greater plane capacitance.
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*> >
*

*> > My questions is this: How does a lack of planar capacitance contribute
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*> > to increasing EMI? It seems that not having the proper plane capacitance
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*> > would tend to slow edge rates and possibly be one of the lesser SI sins.
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*> >
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*> > Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
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*> > decreasing EMI?
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*> >
*

*> > Regards,
*

*> > Matt Stanik
*

*> > PCB Design Engineer
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*> >
*

*> >
*

*> > **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*> [email protected] In the BODY of message put: UNSUBSCRIBE si-list
*

*> or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*> > si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*> > ****
*

*> >
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*> si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*> ****
*

-- Ronald B. Miller _\\|//_ Signal Integrity Engineer (408)487-8017 (' 0-0 ') fax(408)487-8017 ==========0000-(_)0000=========== Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131 [email protected], [email protected]**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****

**Next message:**Ron Miller: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Previous message:**Mayer, Mike: "RE: [SI-LIST] : Fast edges with limited plane capacitance"**In reply to:**Larry Smith: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Next in thread:**S. Weir: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**S. Weir: "Re: [SI-LIST] : Fast edges with limited plane capacitance"

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