Re: [SI-LIST] : ESR and bypass caps

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From: Istvan Novak - Board Design Technology (inovak@pompom.east.sun.com)
Date: Mon Feb 07 2000 - 11:46:53 PST


Hi List,

Some of you may have experienced errors accessing the
http://home.att.net/~istvan.novak/ webpage. As Scott points out below, the
error is related to the fact that the backslashes forward slashes are
interchanged in the links. This was done by FrontPage Editor, and I did not
notice this problem upon testing, because InternetExplorer seemingly took these
links.

Until I get to this problem in the evening, you can simply change the slashes
manually as you encounter the Not Found page error.
(change e.g., the last slash from
http://home.att.net/~istvan.novak/papers\papers.html to
http://home.att.net/~istvan.novak/papers/papers.html).

I am sorry for the confusion.

Istvan Novak
SUN Microsystems

        X-Unix-From: scott@vasthorizons.com Mon Feb 7 01:24:39 2000
        Delivered-To: fixup-si-list@silab.eng.sun.com@fixme
        Date: Sun, 06 Feb 2000 22:15:43 -0800
        From: Scott McMorrow <scott@vasthorizons.com>
        X-Accept-Language: en
        MIME-Version: 1.0
        To: si-list@silab.eng.sun.com
        Subject: Re: [SI-LIST] : ESR and bypass caps
        Content-Transfer-Encoding: 7bit
        
        Istan,
        
        The links on you page are wrong.
        
        There is a backslash instead of a forward slash in
        the links to the presentations and to the tools.
        
        regards,
        
        scott
        
        Istvan NOVAK wrote:
        
> DougS,
>
> As Ray pointed out, Larry's deck was for the single-node analysis. To
> illustrate the effect of capacitor locations, I compiled a short slide
show
> from various simulation results, it is posted in
> http://home.att.net/~istvan.novak/ under illustration tools. On each
page
> there are self-impedance profiles of a 8"x8" plane pair with 2-mil FR4
> dielectrics, with four different conditions: 1) bare planes, 2) 0.1uF
bypass
> capacitors all in the center, 3) the same number of 0.1uF bypass caps
spread
> evenly around the board periphery, and 4) the same number of resistive
> termination evenly spread along the board periphery. From the many
> simulated scenarios probably these four represent the most interesting
> extreme corners. The impedance on a one-inch grid was simulated
between the
> planes and the impedance magnitudes are plotted in ohms. The
successive
> pages correspond to different frequencies. Note that here no attempt
was
> made to smooth out the impedance profile by selecting a range of
capacitance
> values, instead the emphesis was on the variation with capacitor
location.
>
> Istvan Novak
> SUN Microsystems
        
        --
        Scott McMorrow
        Principal Engineer
        SiQual, Signal Quality Engineering
        18735 SW Boones Ferry Road
        Tualatin, OR 97062-3090
        (503) 885-1231
        http://www.siqual.com
        
        
        
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Istvan Novak Sun Microsystems, Inc.
Istvan.Novak@Sun.Com Workgroup Servers, BDT Group,
                        One Network Drive, Burlington, MA 01803
                        Phone: (781) 442 0340

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