Re: [SI-LIST] : on-chip decoupling capacitance (and SI)

About this list Date view Thread view Subject view Author view

From: D. C. Sessions ([email protected])
Date: Tue Apr 18 2000 - 16:51:44 PDT


Sandy Taylor wrote:
>
> > I have heard rumors that modern microprocessors use 10s of nF of on-chip decoupling
> > (presumably provided by large areas of thin oxide) to keep the core supply noise in a
> > range where the flip-flops don't loose their minds.
>
> Chris
>
> For a solution running at 1GHz in a device drawing 80W in a 0.18u technology, look at:
> "An On-Chip Voltage Regulator Using Switched Decoupling Capacitors" in ISSCC 2000.
> I'll see if I can get a copy of the paper and slides for Ray to make available.
>
> The on chip problems can be severe. 100s of nF is a reasonable for a large microprocessor today. This helps provide a reservoir of charge for the surge of current with each clock tick within a clock
> cycle or for a step in the current due to an increase in activity over several cycles. With today's uP, the potential dI/dT is so severe that even using a flip chip ball grid array with hundreds of
> power/ground pins and a carefully designed package you have no chance of seeing significant current from the board for several clock cycles.

Case in point: we just ran the onchip capacitance extraction for a customer
device. 200nm technology, before adding intentional bypass devices, the
assorted sources of supply capacitance came to ~230 nF in the 100-1000 MHz
range.

-- 
D. C. Sessions
[email protected]

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:14 PDT