Re: [SI-LIST] : Fast edges with limited plane capacitance

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From: ajmani@us.ibm.com
Date: Fri Mar 17 2000 - 12:17:08 PST


I have read some excellent comments on this subject from various experts
like Larry Smith, Mike Conn, Doug McKean, and Ron Miller. I would like to
put my $0.02 worth.
Years ago when I was working at an EMC Lab, I tested a 6-layer 386 based PC
motherboard (a rarity those days), with S-S-P-G-S-S stackup. During my
grooming in the EMC field, I too was made to believe that correct 6-layer
stackup had to be S-P-S-S-G-S, and I mentioned this to my customer. To my
surprise, the board passed FCC-B test very easily. More recently, I had
two boards built with same design in two different ways. The design used a
40 MHz clock and 1-2 ns rise time on signals. Board with S-P-S-S-G-S
stackup had slightly lower (within 3 dB) emissions upto 200 MHz, but at
higher frequencies, S-S-P-G-S-S stackup showed superior EMI performance.

In an ideal board, traces shielded within power planes will have lower
emissions. However, the traces have to start and end on top or bottom
surfaces, resulting in an extra pair of vias. Again, emission contained
within shield planes will try to find other outlets, and may couple to the
cables. On the other hand, properly terminated microstrips will have very
low radiation, if one takes good care to route them against an unbroken
plane to ensure good return path. I will route all critical nets
referenced to ground plane only. Hence, I too vote for S-S-P-G-S-S
stackup.

Regards,

Ravinder Ajmani
PCB Development and Design Department
IBM Corporation
Email: ajmani@us.ibm.com
***************************************************************************
Always do right. This will gratify some people and astonish the rest.
.... Mark Twain

mjs <mjs@enteract.com>@silab.eng.sun.com on 03/17/2000 08:29:33 AM

Please respond to si-list@silab.eng.sun.com

Sent by: owner-si-list@silab.eng.sun.com

To: "'si-list@silab.eng.sun.com'" <si-list@silab.eng.sun.com>
cc:
Subject: [SI-LIST] : Fast edges with limited plane capacitance

Let's assume that a power subsystem has a low, flat impedance up to a few
hundred MHz, and has a pair of realtivly unbroken planes. Only problem is
that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
will be a problem unless all noisy digital signals are 'sandwiched'
between the planes. This board also has parts with 1-2ns edge rates.

I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
yielding much greater plane capacitance.

My questions is this: How does a lack of planar capacitance contribute
to increasing EMI? It seems that not having the proper plane capacitance
would tend to slow edge rates and possibly be one of the lesser SI sins.

Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
decreasing EMI?

Regards,
Matt Stanik
PCB Design Engineer

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