Re: [SI-LIST] : interplanar capacitance

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From: sweir (weirsp@a.crl.com)
Date: Thu Feb 03 2000 - 12:49:25 PST


Ewart,

It depends on what you want to spend. You can get 5 mil separation
cheaply, and down to 3 mil for more money without special materials, such
as HADCO. 5 mils approximates 200 pF / sq in.

You might want to think about a stack-up more like this:

L1 Comp
L2 V1
L3 GND
L4 S1 N-S
L5 S2 E-W
L6 GND
L7 V2
L8 S3

You get good plane capacitance for all your supplies, a good set of N-S,
E-W striplines, in S1 and S2, and retain balanced
construction. Unfortunately, you will still have ground currents jump
planes when switching from S1 to S2 and back.

The choice of which voltage to put on L2, and which on L7 depends on your
application. If you are running any PECL off that 5V, then V2 should be
5V, and the PECL signals should run in L8. This leaves 3.3V in V1 which
presents less inductance. I think that you will be best-off placing the
2.5V island for the Virtex part in L2 for the same reason.

Regards,

Steve.

At 02:48 PM 2/3/00 -0500, you wrote:

>Dear List Members,
>
>I have an eight layer board with four routing and four plane layers. The
>stackup I have chosen is;
>
> Primary side (signal) - contains all components
> +5V (full plane)
> Internal (signal)
> GND (full plane)
> +3.3V (full plane)
> Internal (signal)
> GND (full plane)
> Secondary side (signal) - no components
>
>I want to take advantage of the interplanar capacitance between planes GND
>and +3.3V. What core thickness should I specify? At what dimension
>(thickness of core) would I lose this advantage? Also, on the secondary
>side under an FPGA I have a large copper fill area that carries +2.5V, can
>I use the adjacent GND plane and this area fill for more decoupling. If
>so what thickness of prepreg should I specify? I would like to maintain a
>0.062" overall thickness of the PWB.
>
>Thank you all,
>Ewart Speer
>Scientific Atlanta

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