RE: [SI-LIST] : tracking/oversampling PLL architectures

About this list Date view Thread view Subject view Author view

From: Keith Amundsen ([email protected])
Date: Tue Mar 14 2000 - 07:35:21 PST


Jim
I have seen multiple lower-speed PLLs used in parallel to keep clock rates
down but I have never heard of the approach you mentioned.
Regards, Keith

-----Original Message-----
From: Lyke James Civ AFRL/VSSE [mailto:[email protected]]
Sent: Monday, March 13, 2000 3:27 PM
To: '[email protected]'
Subject: RE: [SI-LIST] : tracking/oversampling PLL architectures

Since you mentioned PLLs, I was wondering if you knew what is the best
possible synchronization that can be achieved? I had someone tell me he
thought it was possible to achieve 10 pico-second synchronization by using
a whole bunch of individual PLLs somehow magically tied together , citing
a "square root n" improvement in synchronization as more PLLs are added.
??

jim

> -----Original Message-----
> From: Keith Amundsen [mailto:[email protected]]
> Sent: Monday, March 13, 2000 1:01 PM
> To: '[email protected]'
> Subject: RE: [SI-LIST] : tracking/oversampling PLL architectures
>
>
> A Digital Phase Locked Loop (DPLL) is the oversampling
> variety. They may
> have a tracking mode and a hold mode. In the tracking mode a
> special or
> preamble pattern with maximum transition density is covenant
> to quickly
> determine the bit centers for sampling. Then in the hold
> mode during random
> data, the DPLL is not allowed to adjust anywhere near as
> often. Polynomial
> scrambling circuits, turned on at the data source after the
> preamble ends,
> etc., can be used to help ensure transitions during hold mode.
> Regards, Keith
>
> -----Original Message-----
> From: Ooi, Thien Ern [mailto:[email protected]]
> Sent: Friday, March 10, 2000 8:29 PM
> To: '[email protected]'
> Subject: RE: [SI-LIST] : tracking/oversampling PLL architectures
>
>
> Once the appropriate sample has been determined, how
> frequently does the
> sample choice need to be updated? Is a special data pattern needed to
> update the sample choice, or random data will do, as long as
> there is a
> certain minimum transistion density?
>
> -----Original Message-----
> From: [email protected]
[mailto:[email protected]]
Sent: Thursday, March 09, 2000 1:56 AM
To: [email protected]
Subject: Re: [SI-LIST] : tracking/oversampling PLL architectures

<snipped>

In the oversampling PLL, which technically isn't a pll, a local and
relativly stable clock is used to sample the incoming bitstream several
times during each bit period. Logic then determines on a bit by bit
basis which of the several samples is the one to be used. You don't
actually have to have a local clock that is many times the frequency of
the bit rate, just generate several phases of a clock at the bit rate.

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list
or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE si-list
or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:34 PDT