RE: [SI-LIST] :What do inputs do? monotonic signals at SDRAM-, SSRAM - and FEPROM-a dress inputs

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From: Jonathan Dowling ([email protected])
Date: Thu Feb 24 2000 - 09:09:27 PST


Rich,
I curious to know if the Monte Carlo receiver characterization
described in your presentation required:

A. Full 3-D package models of signal/power/gnd and full PEEC
    interconnect model covering all possible combinations of
    parameters such as Zo, topology, Tpd, etc.

B. 2-D interconnect model of signals and simple package models.

C. No interconnect model at all and only a simple package
    pwr/gnd model.

D. No interconnect model and an elaborate package pwr/gnd
    model.

E. No interconnect model at all and no package pwr/gnd model.

How many folks would agree with statement 1 or 2?

1.
============================================================
It is my experience that no matter how elaborate the circuit
design, ultimately the receiver performance must be
describable in terms of VIH/VIL (VID for differential),
input edge-rate, and common-mode range in order to be
testable and listed in a product datasheet. I guarantee
the receiver performance specs listed in the datasheet and
test each component to this spec.

2.
============================================================
It is my experience that receiver circuit design is so
elaborate and timings so tight that performance can only be
measured in a simulation environment and not in design
characterization and product test. Therefore the product
datasheet specs for receiver requirements are irrelevant.
All attempts at characterizing the receiver performance in
silicon are a waste of time. I only guarantee the receiver
model that I give to customers and not the information in
the product datasheet. Product test will make no attempt
measure receiver performance.

Jonathan Dowling

-----Original Message-----
From: Mellitz, Richard [SMTP:[email protected]]
Sent: Monday, February 14, 2000 9:45 PM
To: '[email protected]'
Subject: [SI-LIST] :What do inputs do? monotonic signals at SDRAM-, SSRAM - and FEPROM-a dress
inputs

Use to be: monotonic signals at SDRAM-, SSRAM- and FEPROM-a dress inputs
... and other similar topic's.

Certain signals are just a SI fact of life. The question to ask is "just
what do these type of signals do to receivers". The answer is "let's just
find out".
I've be asked by a few to post the presentation I did a few weeks ago at the
IBIS Summit in Santa Clara. The follow explains how figure out receivers and
visualize the results. I got the idea from a colleague here at Intel, Alex
Levin, who has done extensive work with the application of Monte Carlo
methodologies.

ftp://63.225.95.1/pub/IBIS_SUMMIT_00_rcvr_modeling.zip
~700KB pdf in zip ...You'll have to figure it out without my babble :-)

Once an analysis is carried out, the information on performance can be used
to create guard bands, specs on monotonic behavior, slew rate dependence,
ringback tolerance, or whatever. Its up to the vendor to determine just how
to use the data, e.g. create a behavioral model, special spec, etc. Also,
the results of this directly affects certain historic timing parameters such
as setup and hold.

The real interesting thing for me was on page 9. Its a response to monotonic
edges. There are "mountains of peril" surrounded by "valleys of
performance". So even with spice, you could get fooled into thinking you had
solid system. This could be the case where the corners you simulated never
bump into the mountains. Maybe this can explain why vendors only define
monotonic signals but users find they work just fine in a given system.

Many of you receiver designers may want to use the method above to give us
poor users a better understanding how we can scrub some picoseconds.

Rich Mellitz,
Intel
 

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