RE: [SI-LIST] : anybody fielding newbie questions??

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From: Peters, Stephen (stephen.peters@intel.com)
Date: Mon Apr 17 2000 - 13:52:06 PDT


Hello Miker:

  I'll take a shot at answering. A board with an odd number of layers
is difficult to manufacture. Basically, to do this means removing
all the copper from one side of a fiberglass panel, thus leading to
warping due to unequal thermal expansion. I suggest a ten layer
stackup as follows:

1. signal
2. GND
3. signal
4. signal
5. PWR (+5)
6. GND
7. signal
8. signal
9. PWR (-15)
10. signal

  With this stackup the adjacent PWR/GND layers (5 and 6) form a
relativly good decoupling cap. Route any signal referenced to the
-15v on layers 8 and 9.

  Regards,
  Stephen Peters
  Intel Corp.

> -----Original Message-----
> From: Robison Michael R CNIN [mailto:Robison_M@crane.navy.mil]
> Sent: Monday, April 17, 2000 1:13 PM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : anybody fielding newbie questions??
>
>
> hello,
>
> i hope that i'm posting correctly here. i'm laying out a board and
> thinking i'll have 9 layers:
>
> sig
> +5V
> sig
> sig
> gnd
> sig
> sig
> -15V
> sig
>
> this means my power and ground planes aren't adjacent, but at
> least each signal is positioned next to a power/gnd plane. the
> board is 11" by 11" and running ALS for some lowspeed memory
> loading and memory access, and then a few F series chips to
> run at 25MHz, with some of the fast stuff as board I/O.
>
> any comments would be appreciated.
>
> thank you, miker
>
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