From: S. Weir ([email protected])
Date: Sun Mar 19 2000 - 03:00:55 PST
This subject thread has certainly gotten interesting.
As one who has previously made the mistake of using the inverse square
formula for plate capacitors for longer than I care to admit, I feel
compelled by "12 steps" to point-out that the accepted formula is inverse
proportion to the plate separation. Any college physics text such as
Resnick and Halliday confirms this as the definition of capacitance as an
observed phenomenon is based on the plate capacitor equation.
Review of the same text supports Larry' Smith's contention for the increase
in mutual inductance. When the plates are brought closer together, the
magnetic fields caused by current flow are also closer, the magnetic path
length is shorter, the flux density and mutual coupling are both higher.
At 11:13 AM 3/17/2000 -0800, you wrote:
>I have some issues as follows
>>So, if we compare the two power plane pairs below with 4 and 40 mil
>> The velocities are constant.
>> The capacitance of the 4 mil planes is 10X the 40 mil plane.
>Capacitance as you mentioned above is proportional to the inverse of the
>square of the distance making 4 mils 100 X the 40 mil plane.
>> The inductance of the 40 mil plane is 10X the 4 mil plane.
>The inductance does not change with dielectric thickness. In fact if you
>look at a smith chart you will note that the low impedance outside circles
>tend to approximate the outer circle as you go out. The outside circle
>follows the electrical length and cannot be made larger then the length
>of the line. This is a limit.
>> The impedance of the 40 mil plane is 10X the 4 mil plane.
>The impedance normally used for traces proportional to W/H might
>be used as a basis for comparing low frequency signals, and therefore
>this would hold. However, for a wide plane, and a high frequency
>signal, the capacitance a quarter wavelength out has no effect and so
>also the impedance effect. As the width approaches the quarter wavelength
>of the frequency under consideration the impedance decreases at a
>squared rate of the proportion of width to quarter wavelength with the
>>To directly answer Mark's questions, with the same amount of noise
>>stimulation, there will be much more noise between the 40 mil power
>>planes than between the 4 mil planes, in fact 10X. The reason is
>>because of the increased impedance.
>Total capacitance will be 100 times
>Xc will be 1/100
>Since P=E*2/Z, P being constant
> E=Sqrt(P/Z) substitute Xc for Z
> E=Sqrt(1/Z) = 1/10
>Yes the apparent noise voltage for 4 mils is 1/10 the voltage at 40 mils.
>>It turns out that one of the most important consequences of thin power
>>planes is the 10X decrease in inductance. This greatly increases the
>>effectiveness of the discrete decoupling capacitors that are mounted on
>>the power planes.
>Cant buy this.
>>I vote for the s-s-G-P-s-s stackup. Not only does it have better
>>capacitance properties, but it also has better inductance and impedance
>>properties. SI and EMI noise are greatly reduced. Microstrip
>>transmission lines work just fine.
>For minimum crosstalk, ground bounce and supply sag this is the best
>because the G-P layers can be made thinner as noted.
>However, for minimum EMI, sandwiching the traces internally between
>the power/ground planes may be preferrable.
>Sorry we do not agree.
>> > Date: Fri, 17 Mar 2000 10:29:33 -0600 (CST)
>> > From: mjs <[email protected]>
>> > To: "'[email protected]'" <[email protected]>
>> > Subject: [SI-LIST] : Fast edges with limited plane capacitance
>> > MIME-Version: 1.0
>> > Let's assume that a power subsystem has a low, flat impedance up to a few
>> > hundred MHz, and has a pair of realtivly unbroken planes. Only problem is
>> > that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
>> > will be a problem unless all noisy digital signals are 'sandwiched'
>> > between the planes. This board also has parts with 1-2ns edge rates.
>> > I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
>> > allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
>> > yielding much greater plane capacitance.
>> > My questions is this: How does a lack of planar capacitance contribute
>> > to increasing EMI? It seems that not having the proper plane capacitance
>> > would tend to slow edge rates and possibly be one of the lesser SI sins.
>> > Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
>> > decreasing EMI?
>> > Regards,
>> > Matt Stanik
>> > PCB Design Engineer
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>Ronald B. Miller _\\|//_ Signal Integrity Engineer
>(408)487-8017 (' 0-0 ') fax(408)487-8017
>Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131
>[email protected], [email protected]
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