From: Chris Cheng (email@example.com)
Date: Fri Mar 17 2000 - 15:07:35 PST
i would pick the s-G-s-s-P-s because i believe the power system
response is slow that all the switching current will be coming
from and returning to the local decoupling capacitors. unless
you are using exotic decoupling capacitors, your lead and pad
inductance on the capacitor will be so dominance over the
plane loop inductance that it doesn't really matters whether
the plane loop inductance is off by a factor of ten as long
as the decoupling capacitor location is reasonable close to
on the other hand if you use s1-s2-G-P-s3-s4, s3 and s4 will
have no reference to ground and the signal return current
will generate significant common mode noise on both the signal
and the power plane that it will be both a SI and EMI problem.
of course this assume the i/o system has a pull down drive or
is open drain to ground.
From: mjs [mailto:firstname.lastname@example.org]
Sent: Friday, March 17, 2000 8:30 AM
Subject: [SI-LIST] : Fast edges with limited plane capacitance
Let's assume that a power subsystem has a low, flat impedance up to a
hundred MHz, and has a pair of realtivly unbroken planes. Only problem
that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
will be a problem unless all noisy digital signals are 'sandwiched'
between the planes. This board also has parts with 1-2ns edge rates.
I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
yielding much greater plane capacitance.
My questions is this: How does a lack of planar capacitance contribute
to increasing EMI? It seems that not having the proper plane capacitance
would tend to slow edge rates and possibly be one of the lesser SI sins.
Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
PCB Design Engineer
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