From: Dave Hoover (firstname.lastname@example.org)
Date: Mon Apr 10 2000 - 16:48:22 PDT
I don't know if people answered this directly or if Mitch's
answer was the main input. From a fabrication stand point,
this is a serious concern. Fabricators make plating thieving
requests all the time. Some OEM specifications actually give
the fabricator the right to just add/modify the outerlayer
artwork/images in order to increase process yields during
the manufacturing of the PCBs. :-/ (Plating Thieving Only)
99 % of the Time The Fabricator Does Not Understand the
Electrical Design Intent.
Issue: It's very important that if the thieving
is added, that it does not create additional electrical
performance changes. I have seen plating thieving on outerlayers
effect the single ended impedance on layer 2. The isolated
plating thieving on layer 1 was directly over critical inboard
test coupon traces on layer 2. I measured Zo which indicated
too low and removed the squares. Retested the lyr 2 test structure
which was then within spec. :-/ When the fabricator runs his plating
thieving scripts, it's best to have lyr 1 and 2 merged when
generating those images. I was told that if the plating thieving
was either too close to critical traces or was not broken up
squares <isolated> then something called "the antennae effect"
would be produced. (Albeit this falls into one of those coined
Another hugh concern would be prototype versus production runs.
With some of today's faster logic speeds, one might want to highly
consider possible differences between a prototype PCB which may
not have any plating thieving added versus a production tooled
run that might have had the plating thieving added.
In Summary: Best to review any proposed changes from the
fabricator (Plating Thieving Included).
Make sure that when they do generate plating thieving images,
they include all applicable signal line images that represent
what's beyond the outermost plane. (e.g., if lyr 1 and 2 were
signals and 3 was a plane, merge layers 1 and 2 <temporarily>
to generate the plating thieving image to be added to layer 1.)
Make sure the prototype run represents what will be used on the
BTW-Digital ground pours, max copper outerlayers, or outerlayer
mesh planes makes this a moot point. There will be no need to
add any thieving on those types of images.
Just my 2 cents.......
From: email@example.com [mailto:firstname.lastname@example.org]
Sent: Wednesday, March 08, 2000 12:05 PM
Subject: Re: [SI-LIST] : Hatch
>Date: Wed, 08 Mar 2000 12:53:37 -0500
>From: "DORIN OPREA" <email@example.com>
>Subject: [SI-LIST] : Hatch
>I try to understand the hatch EMC effect on the PCB,
>whether this floating copper required for the copper
>balance is a EMC problem for high speed design
>or not and what will be the limit it start to be one.
I have seen both sides of the fence, without any "real" data either way
to proved the hypothetical question "Does it affect the design". I know
many boards where the fab house has hatched or added copper shapes
(round pads or ovals, etc) to the outer layers to help balance the
copper for plating up the copper, and I've seen a few where the fab
houses has asked to add copper to the internal signal layers for etching
concerns, but I've never seen the data to proved it's detrimental to the
circuit design. I've had one engineer that would allow it, only on the
external layers, but asked to fab shop to hold it back .300" from any
design feature (pads, traces, etc). I'm fairly certain the fab shops
hold it back .100" minimum as a practice, and it's extremely easy for
them to do in their CAM tools, and it tends to help their
Sr PCB Designer
San Diego, CA
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