Re: [SI-LIST] : width of the return path

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From: Nirmal Jain (nirmalj@pacbell.net)
Date: Sun Jan 16 2000 - 11:38:15 PST


Hi Teddy,

In addition to Eric's paper, there was one presented at ECTC 94 by Prof. John Prince.
I don't remember the title but may be somebody on the board remembers it.
Hope it helps you in analyzing your designs.

Best regards

Nirmal

Eric Bogatin wrote:

> Teddy-
>
> You are asking about the width of the return path for microstrip and
> stripline structures. The quick answer is to reach a characteristic
> impedance value within 1% of an infinitely wide return path, use a return
> path width that extends at least 3xh on either side of the signal trace
> width, with h the thickness of the dielectric. For example, an 8 mil wide
> microstrip with 4 mil thick dielectric should have a return path width at
> least 3 x 4 = 12 mil wide on either side of the trace, for a total width of
> 12 + 8 + 12 = 32 mils. Making it narrower than 32 will typically increase
> the characteristic impedance.
>
> For more details on this, please see the paper I presented at DesignCon99.
> It is available for download from my Sept 99 downloads on my web site, if
> you check in the publications section.
>
> As a side note, if you are trying to do transmission line design for PCB
> stack up for example, I would recommend using a 2D field solver, rather than
> a 3D solver. It will run faster, and the Ansoft Maxwell 2D Extractor, part
> of the SI2D suite, will be more accurate.
>
> --eric
>
> Eric Bogatin
> BOGATIN ENTERPRISES
> Training for Signal Integrity and Interconnect Design
> 26235 W. 110th Terr.
> Olathe, KS 66061
> v: 913-393-1305
> f: 913-393-1306
> pager: 888-775-1138
> e: eric@bogent.com
> web: <http://www.bogatinenterprises.com/>
>
> > -----Original Message-----
> > From: owner-si-list@silab.eng.sun.com
> > [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Teddy Chou
> > Sent: Friday, January 14, 2000 3:48 AM
> > To: 'si-list@silab.eng.sun.com'
> > Subject: RE: [SI-LIST] : questions about Spicelink/Ansoft tools
> >
> >
> > Dear Nirmal,
> >
> > Thanks for your response. I've got many suggestions from your
> > company. Thanks for all.
> > One of these suggestions is that, for the return path of microstrip
> > lines, a 10% more in the width of the ground plane than the trace is
> > enough. For different structures, we often need to select or build an
> > adequate return path model by ourselves. Why can't this tool help us
> > to do that according to its field distribution or something else?
> >
> >
> > Best regards,
> >
> > Teddy Chou(Hou-Yuan Chou)
> > Signal Integrity Engineer,
> > VIA Technologies, Inc. Taipei, Taiwan, ROC
> > TEL : 886-2-22185452 ext : 6046
> > mailto:teddychou@via.com.tw
> > Very Innovative Architecture
> >
> >
> >
> >
> > -----Original Message-----
> > From: Nirmal Jain [mailto:nirmalj@pacbell.net]
> > Sent: Tuesday, January 11, 2000 3:33 AM
> > To: si-list@silab.eng.sun.com
> > Subject: Re:[SI-LIST] : questions about Spicelink/Ansoft tools
> >
> >
> > Dear Teddy,
> >
> > When you use "Return Path" in Maxwell Quick 3D Extractor, it is actually
> > computing loop inductance assuming the return current is flowing through
> > the
> > assigned return path conductor. So if I have a signal conductor over a
> > gnd plane, the original matrix would look like
> >
> > L11 L12
> > L21 L22
> >
> > where L11 represents the partial inductance of the signal conductor, L22
> > is the partial inductance of the gnd plane and L12 (or L21) represents
> > the mutual
> > inductance between the signal conductor and the gnd plane.
> >
> > When you use "Return Path" operation, the software is computing the loop
> > inductance using the expression
> >
> > Lloop = L11 + L22 - 2 * L12
> >
> > The Loop inductance would be higher than the partial inductance of the
> > signal conductor if
> >
> > 1) Ground plane is far off, hence my L12 is very small
> > 2) or if my mutual inductance number is negative in the original matrix,
> > which means when I do my return path operation, my current in the gnd
> > plane is not
> > flowing in the opposite direction to the current in the signal
> > conductor. In this case the L12 term would added instead of being
> > subtracted ( negative of
> > negative is +ve). So if your mutual number is -ve, you could either
> > re-solve the model by swapping sink/source terminal or swapping the
> > sink/source
> > terminals in the reduce matrix operation. I prefer the reduce matrix
> > step as it is much faster. After this operation, the mutual between the
> > gnd plane and
> > the signal should be +ve, and it would actually get subtracted in the
> > return path operation instead of being added and you would see a much
> > lower number!
> >
> > 3) the solution may not be converged
> >
> >
> > Hope it helps. Let me know if you have any further questions. If you
> > still have problems feel free to send me the model.
> >
> > Best regards
> >
> > Nirmal
> >
> >
> > > > -----Original Message-----
> > > > From: Teddy Chou
> > > > Sent: Friday, January 07, 2000 11:00 AM
> > > > To: 'hfss@cee.hw.ac.uk'
> > > > Subject: HFSS: questions about Spicelink/Ansoft tools
> > > >
> > > > Hi,
> > > > Recently, I have started to use the Spicelink / Ansoft
> > > > simulation tools( it resembles the HFSS/Ansoft, but only the
> > > > quasi-TEM waves guided by transmission lines are
> > > > considered ). I found some problems when using the
> > > > "REDUCE MATRIX" item in Maxwell 3D Extractor. I needed to
> > > > get some characteristics of microstrip lines. However, when I
> > > > assigned the ground plane to the "return path" or "ground"
> > > > ( part of the return path ), the inductance would increase as
> > > > the size of ground plane increases. Even when the ratio of
> > > > the width of ground plane and the width of a trace is over 100,
> > > > it never got a stable value. For avoiding this phenomenon, I
> > > > tried to decrease the area of the I_sink and I_source surface
> > > > in the ground plane, it still got the resembling results. Who can
> > > > tell me how to assign the reasonable size of the ground plane
> > > > for microstrip lines.
> > > >
> > > >
> > > > Best Wishes,
> > > >
> > > > Teddy Chou
> > > > Signal Integrity Engineer,
> > > > VIA Technologies, Inc. Taipei, Taiwan, ROC
> > > > TEL : 886-2-22185452 ext : 6046
> > > > mailto:teddychou@via.com.tw
> > > > Very Innovative Architecture
> > > >
> > > >
> >
> > Nirmal Jain
> > Senior Application Engineer
> > Signal Integrity Products
> >
> >
> > Ansoft Corp.
> > 2560 Oak Rd. #322
> > Walnut Creek, CA 94596
> > (925) 938-6490 (Tel)
> > (925) 215-2477 (Fax)
> >
> >
> > Pittsburgh Office:
> >
> > Four Station Square
> > Pittsburgh, PA 15219
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> >
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