RE: [SI-LIST] : HSPICE Start Up conditions

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From: Tom Dagostino (tom_dagostino@mentorg.com)
Date: Wed Mar 22 2000 - 10:50:21 PST


One thing I would look at is the output impedance of the driver. With the
4.5K pull down there is little standing current keeping Zout high (I'm
assuming and ECL like driver). During the falling transition the transistor
is off and the 4.5K is the source of current.

Tom Dagostino
ICX Modeling Group
tom_dagostino@mentor.com
503-685-1613

    -----Original Message-----
    From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Kai Keskinen
    Sent: Wednesday, March 22, 2000 7:46 AM
    To: 'si-list@silab.eng.sun.com'
    Subject: [SI-LIST] : HSPICE Start Up conditions

    Hi SI Folk:

    I had a lot of problems getting a spice model of a gigabit ethernet chip
to run properly. The differential outputs are tied to ground with 4.5kOhm
resistors and then coupled to the long T-lines (W-element) with ~1nF caps.
They are terminated with 100ohms across the differential pairs just before
the receiver. It turned out that if we did not set the initial charging
conditions on the coupling caps to a very narrow range of values, the
simulation never actually worked. One or both of the differential outputs
did not at all resemble what the chip should transmit even for very long
simulation times.

    My questions are: Why did the circuit not charge up the caps and then
work as would happen in reality? Is this a very common effect when running
HSPICE or other sims?

    Thanks,

    Kai Keskinen
    Equipment and Network Interconnect
    Nortel Subsystems and Performance Networks (NSPaN)
    (613)-765-3506 (ESN 395)
    keskinen@nortelnetworks.com

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