From: Netzler Dirk (Dirk.Netzler@icn.siemens.de)
Date: Tue Mar 07 2000 - 07:05:14 PST
what about radiation when fast signals (or at least signals with fast ramps)
on outer layers ? EMI could be a problem.
Therefore I prefer the following layer stackup:
with PWR (4) and GND (3) close together (<=100um).
Okay, I admit, 6 layers are more expensive than 4 layers.
> -----Ursprüngliche Nachricht-----
> Von: Fred Dehkordi [SMTP:FredD@texasmicro.com]
> Gesendet am: Dienstag, 7. März 2000 15:43
> An: 'email@example.com'
> Betreff: RE: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?
> I don't see that much of draw back. The only thing must be consider is the
> control impedance of these signals routed on outer layer. Those signal
> routed in outer layer might get about 90 ohm control impedance and as far
> I remember, PCI signals impedance match about 50-80 ohm. This is still
> possible by adding discrets to the circuitry and some smart engineering
> Just a reminder, routing SCSI signals on outer layers are a good move
> because these signals require about 100 ohm control impedance.
> Best Regards,
> Fred Dehkordi
> Design Engineer
> Radisys Corporation
> Communication Platforms Division
> Tel : (713) 541-8200 Ext # 244
> Email : firstname.lastname@example.org
> > -----Original Message-----
> > From: Alex Li [SMTP:email@example.com]
> > Sent: Monday, March 06, 2000 8:36 PM
> > To: 'firstname.lastname@example.org'
> > Subject: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?
> > Recently I saw a 4-layer mother board with 100 Mhz 128-bit memory bus.
> > This board has unusual signal-power-ground-signal stack up. I talked
> > one of their engineer for this kind of arrangement. They said since
> > PC motherboard has several power plane split and on the top level there
> > are a lot of components with pads. they think if they route all the
> > 128-bit memory bus on the back and put it close to ground plane, they
> > much routing area and this will help to keep the signals clean.
> > This is kind of new idea to me, does anyone see any drawback by
> > arrangement ? Will this decrease the decoupling caps performance ?
> > Alex
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