Re: [SI-LIST] : Gigabit eithernet board.

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From: Dennis Tomlinson (det@tellabs.com)
Date: Mon Feb 07 2000 - 12:31:49 PST


Nick,

The guys down the road vote for option #1. You might
consider switching the order of the two power layers
to get a bit lower inductance for your 3.3V-IO high-f
decoupling.

Also, don't worry about a few vias. You'll need some
distributed around to stitch the two GND planes
together (to facilitate return paths), and some more
for the decoupling caps (placed to facilitate return
current jumps GND <-> PWR, and device decoupling at
< 250 MHz or so).

Any more Q's, you know where we're at.

DT & SM

(Hi to JB, MJ, RG, & ME)

nick@apptel.com wrote:
>
> Hi. I've been reading this list for several months now, but I still can't
> figure out what to do now. I'm a new engineer working on a new board on
> which I am trying to minimize noise. Cost is not a driving issue.
>
> The board is probably routable on two layers. It has a 3.3V-IO / 2.5V-CORE
> FPGA communicating with two 5v transceiver chips. I am trying to figure out
> how to do the stackup for low noise up to the 1500 Mbaud-serial /
> 100?MHz-parallel speeds that the board will be running at.
>
> I'm thinking option 1:
>
> Top (routing, and ground copper under the transceivers)
> GND (full plane)
> POWER (+5v under transceivers/2.5v under FPGA)
> POWER (3.3v full plane)
> GND (full plane)
> Bottom (routing and capacitors)
>
> This is my take on option 1: All of the signals will route with minimal
> vias on the outer layers, which might be bad for emissions. The board is
> only 3 inches by 4 inches, with the fastest signals moving about an inch or
> so, so this should not be terribly bad.
>
> All the signals will be directly adjacent to a solid ground plane, thus
> eliminating traces passing from the 5v area to the 2.5v/3.3v area. This
> should allow a good return path for all of the signals on top and bottom.
>
> Is this a reasonable stackup?
>
> Would it be significantly better or worse to put in a bunch more vias and
> do something like this (option 2):
>
> Top (minimal routing, ground copper under the transceivers)
> POWER 3.3V
> GND (full plane)
> Routing
> ROUTING
> GND (full plane)
> POWER (5v under transceivers/2.5v under FPGA)
> Bottom (minimal routing)
>
> This puts a 3.3v plane underneath all the components, even the 5v parts. Is
> that a problem? Would it be better to put the split 5v/2.5v plane as the
> second layer? Would it be better to switch the power layers in some other
> order? (e.g. GND on layer 2 and 3.3v on layer 3, or 5v/2.5v split on layer
> 2? and 3.3 on layer 7)
>
> Would the capacitance between the top layer grounded copper and the 3.3v
> plane in option 2 be a bad thing since the transceivers are 5v parts?
>
> We are not as worried about emissions as we are about having a board that
> works reliably (=quietly). It will run inside a PC, so noise coming from
> off the board may be a consideration.
>
> Any more light you can shed on this issue will help a lot.
>
> Nicholas Dietz
>
> ---
> Nicholas Dietz
> Applied Telecom, Inc.
> 3060 Ogden Avenue, Suite 300
> Lisle, IL 60532-1690
> (630) 357-9290 x 219
>
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