From: D. C. Sessions (email@example.com)
Date: Wed Apr 19 2000 - 11:57:41 PDT
"Zabinski, Patrick J." wrote:
> > > > Case in point: we just ran the onchip capacitance extraction
> > > > for a customer
> > > > device. 200nm technology, before adding intentional bypass
> > > > devices, the
> > > > assorted sources of supply capacitance came to ~230 nF in the
> > > > 100-1000 MHz
> > > > range.
> > >
> > > D.C.
> > >
> > > Can you shed some light as to what you mean by "assorted
> > > sources of supply capacitance"? It's hard for me to believe
> > > 230 nF of trace/grid-capacitance, so I'm struggling to figure
> > > out where it's coming from.
> > Most of your logic is quiescent. RAMs especially. And when
> > you get down to it, that means that you have a great deal
> > of gate-source capacitance in series with fully-on source-drain
> > paths. The net effect is a truly enormous amount of charge
> > reservoir, damped by parallel high-ESR drain-well and
> > well-substrate capacitance.
> Thanks; this helps.
> I can understand and reasonably-estimate the effects of the "gate-source
> capacitance in series with fully-on source-drain paths" without
> too much difficulty with Spice. However, I have yet to see an effective
> model within Spice/Hspice that acocunts for the "high-ESR
> drain-well and well-substrate capacitance"; how do you
> determine the effective capacitance for these well-capacitances
> and the associated ESR?
Wet-thumb triangulation from a couple of points. First off, the
well-substrate junctions are very well understood -- we have excellent
control over their doping profiles and know to a fine degree what their
areal capacitance is. Secondly, we can measure it on testers at low
frequencies. Finally, we don't give a flip what the exact values are
so long as we can run plausible back-of-the-envelope calculations to
convince ourselves that there's enough loss in the system to keep the
-- D. C. Sessions firstname.lastname@example.org
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