Re: [SI-LIST] : Power Plane for Internal Device Power?

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From: Bradley S Henson (bhenson@notes.west.raytheon.com)
Date: Thu Jan 27 2000 - 12:56:22 PST


To which I might add that on higher power chips with BIST, you really need to
watch the start-up and stopping of BIST WRT CORE power supply transients. I
suppose sleep modes could also possibly cause some pretty good core transients
on higher power chips. Part of my decoupling checklist always includes checking
for worst case core power transients caused by test or other operation.

Brad Henson, Raytheon

"D. C. Sessions" <dc.sessions@vlsi.com> on 01/27/2000 12:18:52 PM

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 Subject: Re: [SI-LIST] : Power Plane for Internal Device
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"phelan, tony" wrote:
>
> If I have a device whose I/O are 3.3V and internal logic is powered from
> 1.8V do I need a power plane to supply that 1.8V or will a power strip to
> that device suffice? Another way of asking this I guess would be: Are all
> return path currents for the internal 1.8V signals handled internally to the
> device. If so then there would be no advantage to making the 1.8V supply a
> plane?

The answer is (as usual) "It depends."

Depending on the design of the I/O predrivers, there may be some pretty large
transient currents between the core and I/O supplies that show up as honking
high-frequency spikes on the core supply.

Another source of core transient current is power management. Although
indidual clock transients have to be supplied from on-chip capacitance,
power-management and to a lesser extent ordinary data-dependent variations
can cause variations in core current large enough to make trouble if they
show up on long signal-type trace inductances.

--
D. C. Sessions
dc.sessions@vlsi.com

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