Re: [SI-LIST] : Terminator location with larger BGA's

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From: Bob Lewandowski (blewandowski@vixel.com)
Date: Fri Apr 07 2000 - 18:52:17 PDT


I agree, it's usually better to put a capacitive discontinuity (device input) across the line ahead of the termination than to put it at the end of a stub line beyond the termination. Capacitors at the
end of a stub get significantly enhanced (multiplied) by the line length of the stub. If you put the capacitive discontinuity on the line ahead of the termination you can make some effort to compensate
for it by raising the line impedance by narrowing before and after.

---Bob Lewandowski

Ron Miller wrote:

> A technique which though sub-optimal, helps is to run the traces through the
>
> chip pads and continue on to an open area, terminating there. What happens
> is you get a capacitve glitch on the TDR a few picoseconds before the term.
>
> ron miller
>
> > -----Original Message-----
> > From: mcgiffb@ttc.com
> > Sent: Friday, April 07, 2000 1:17 PM
> > To: si-list@silab.eng.sun.com
> > Subject: [SI-LIST] : Terminator location with larger BGA's
> >
> > We are using some 484 pin BGA's (FPGA's), which have edge rates of about
> > 170ps.
> > Using a series termination, it would have to be placed within 1/10 of the
> > transition length according to Howard Johnson. On FR4, the transition
> > length
> > would be .98, making the distance from source to termination .098. It is
> > not
> > possible to get all of the required termination's within that distance.
> >
> > Aside from slowing down the edges (not desirable), waiting longer for
> > things to
> > settle, or going with buried resistance, are there any other solutions for
> > placement of termination's? How are other people terminating large, high
> > pin
> > count devices?
> >
> > Thanks
> >
> > Bill McGiffin
> >
> >
> >
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