**From:** Istvan NOVAK (*[email protected]*)

**Date:** Fri Jan 28 2000 - 04:06:29 PST

**Next message:**Ray Anderson: "Re: [SI-LIST] : Questions abt Power Distribution System"**Previous message:**Peterson, James F (FL51): "RE: [SI-LIST] : Power Plane for Internal Device Power?"**In reply to:**Chang, Isaac Yew Beng: "[SI-LIST] : Questions abt Power Distribution System"**Next in thread:**Ray Anderson: "Re: [SI-LIST] : Questions abt Power Distribution System"

Mr. Chang,

I am sure Ray will answer all of your questions, but since it is probably a

couple of more hours until he sees your message, let me offer my thoughts on

questions 1 and 2.

You can calculate the impedance of a real-life capacitance with a series

RLC, for bypass applications we usually neglect the parallel resistance.

The impedance of the series RLC is Z(jw)=R+j(wL-1/(wC)). If you have two

capacitors, you can add the admittances and take the inverse of it

Z=1/(1/Z1+1/Z2), where Z1 and z2 are the two Z(jw) functions as above. These

are complex numbers, and you can calculate/plot the impedances/admittances

either with SPICE, or in this simple case of having just a few parallel

capacitors, you can use a spreadsheet or MATLAB or something similar to do

the calculation and plotting. You can download a small Microsoft Excel

spreadsheet for this purpose from http://home.att.net/~istvan.novak/

More detailed spreadsheets with up to 10 parallel capacitors and with

automatic statistical tolerance calculation is also available, let me know

if you want it.

Istvan Novak

SUN Microsystems

----- Original Message -----

From: Chang, Isaac Yew Beng <[email protected]>

To: <[email protected]>

Sent: Friday, January 28, 2000 2:50 AM

Subject: [SI-LIST] : Questions abt Power Distribution System

*> Raymond Anderson,
*

*>
*

*> I've read your paper on Power Distribution System Design Methodology and
*

*> Capacitor selection for Modern CMOS technology. I found it excellent and
*

*> well written. I hv some questions here regarding to the topic.
*

*>
*

*> 1. From figure 12(showing the anti-resonance of parallel caps), how do you
*

*> add up two Z-Freq response graphs to get the anti-resonance?
*

*> 2. Say I got the R and X values of a cap for various freq(100, 1K, 10K,
*

*> 100K, 1MHz), say, how can I plot out the Z vs Freq graph for 2 caps(same
*

*> question as above, but it's actually asking how to calculate it and put it
*

*> on a graph)?
*

*> 3. For the formula in estimating the needed decoupling capacitance for a
*

*> PDS, ie. C=I(dt/dv), how do you estimate I and dt here? I is the transient
*

*> current, is it the Imax in the system? dt is the VRM respond time, how do
*

*> you get dt? Is it from the VRM spec or somewhere else?
*

*> 4. Do you do a 'anti-resonance' and Ztarget check at then end of your
*

*> simulation for PDS?
*

*>
*

*> Isaac Chang
*

*>
*

*>
*

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**Next message:**Ray Anderson: "Re: [SI-LIST] : Questions abt Power Distribution System"**Previous message:**Peterson, James F (FL51): "RE: [SI-LIST] : Power Plane for Internal Device Power?"**In reply to:**Chang, Isaac Yew Beng: "[SI-LIST] : Questions abt Power Distribution System"**Next in thread:**Ray Anderson: "Re: [SI-LIST] : Questions abt Power Distribution System"

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