**From:** D. C. Sessions (*[email protected]*)

**Date:** Wed Jan 05 2000 - 13:00:37 PST

**Next message:**Douglas McKean: "Re: [SI-LIST] : What's your favorite Screwy SI Concept?"**Previous message:**Hank Zauderer: "[SI-LIST] : Update on SI manager position..."**In reply to:**Larry Smith: "[SI-LIST] : low ESR decoupling capacitors"**Next in thread:**Larry Smith: "Re: [SI-LIST] : low ESR decoupling capacitors"

Larry Smith wrote:

*>
*

*> Doug - I am changing the thread title to better reflect the subject.
*

*> We need to take a look at inductance, resistance and capacitance
*

*> to determine the impedance of a capacitor at 200 MHz. If you follow
*

*> this through, you will see the great value of low ESR capacitors.
*

*>
*

*> Inductance is probably the most important parameter of a decoupling
*

*> capacitor. You have correctly calculated the inductive reactance of a
*

*> typical capacitor at 200 MHz if it is mounted on 5 nH pads. But with
*

*> careful pad and via design, we routinely reduce the mounted loop
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*> inductance of 0805 size capacitors to less than 1 nH. One nH gives us
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*> 1.26 Ohms of inductive reactance at 200 MHz.
*

*>
*

*> But, suppose we mount a 633pF capacitor with 100mOhms ESR on that 1 nH
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*> pad. It forms a nice series RLC circuit that has a minimum impedance
*

*> at frequency 1/(2pi*sqrt(LC)) = 200 MHz. The impedance is:
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*>
*

*> R + jwL + 1/jwC
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*> = 100m + j 1.26 - j 1.26
*

*> = 100mOhm
*

The problem is that most of us aren't trying to draw narrow-bandwidth

sinusoidal power from the supply network. For us, the wild resonant

swings on the capacitors aren't neatly balanced by equally wild di/dt

swings on the inductance, and instead the local supply gets sucked

down hard at clock edges and then swings out of safe operating area

in between.

I'm somewhat familiar with the work being done on resonant clock/power

systems, but since our libaries and processes aren't designed with

them in mind I really would prefer a supply net that minimized peak

excursions from nominal over one that was nominal only at selected times.

*> By using a low ESR capacitor, we have presented an impedance to the
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*> power distribution system that is 1/10 of the impedance from the
*

*> inductance.
*

*>
*

*> This is an extremely powerful concept. With low inductance mounting
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*> pads and low ESR capacitors, it is possible to build a high performance
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*> power distribution system with a fraction of the capacitors you might
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*> have thought you needed. You just have to carefully pick the
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*> capacitance value, carefully design the pads, and have a source of low
*

*> ESR caps. THE LOWER, the BETTER!
*

*>
*

*> We are designing power distribution systems with target impedances that
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*> are less than 10 mOhms. Typical NPO and X7R capacitors in the 470 pF
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*> to 10 nF range have ESR greater than 100mOhms. We could use capacitors
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*> that have 1/10 the ESR of today's caps. We could reduce the number of
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*> capacitors cluttering up or boards from hundreds to tens. If we only
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*> had lower ESR caps...
*

*>
*

*> We do not sprinkle in capacitors like salt and pepper but rather have a
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*> very deliberate design methodology. It is documented in the IEEE Journal
*

*> Transactions on Advance Packaging, Aug 1999, Vol 22, Number 3. The
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*> paper gives much more details on power distribution and decoupling
*

*> capacitors than I can give in this space. A soft copy is available at:
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*>
*

*> http://www.qsl.net/wb6tpu/si_documents/docs.html
*

*>
*

*> Parallel capacitor resonance is definitely an issue. You must have a
*

*> methodology that avoids the parallel resonance if you are going to use
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*> low ESR capacitors. You must carefully design the power plane stackup.
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*> Placement is critical for capacitors that resonate at a frequency where
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*> the dimensions of the board become significant. But fortunately,
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*> software tools will soon become available in the public domain to help
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*> us do all of this.
*

*>
*

*> Now, all we need is low ESR caps.
*

*>
*

*> BTW, I really like your time domain method of measuring capacitor
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*> parameters. You won't get any information about mounted inductance
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*> from this measurement, but capacitance, ESR and fixture inductance
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*> determine the shape of the observed waveform. Is there some reason
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*> why you use a 100 Ohm resistor to inject energy into the cap? A 50
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*> Ohm resistor might better terminate the transmission line and avoid
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*> transmission line resonance issues in the measurement.
*

*>
*

*> regards,
*

*> Larry Smith
*

*> Sun Microsystems
*

*>
*

*> > Hi All,
*

*> >
*

*> > I just did a "back of the envelope" (literally) calculation assuming a
*

*> > capacitor with 5 nH of inductance. At 200 MHz we get an inductive
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*> > reactance of:
*

*> >
*

*> > 2pi*200*(10**6)*5*10**-9 ~ 6 Ohms!
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*> >
*

*> > I am sure many of us have seen the charts of impedance of bypass
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*> > capacitors and as the calculation above shows, inductive reactance
*

*> > dominates at today's high frequencies. Given this it would seem
*

*> > reasonable to design a capacitor with ESR of a few Ohms if high
*

*> > frequency performance (read that as low ringing) is what is necessary.
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*> > The capacitor's total impedance will be only slightly effected. If you
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*> > are depending on the capacitor furnishing big slugs of current in the
*

*> > 10 MHz range, then ESR should be as low as possible.
*

*> >
*

*> > The net result to me is that ESR should be designed into (or out of)
*

*> > the bypass caps depending on what your requiements are. We tend to
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*> > sprinkle bypass caps on boards like salt and pepper. They probably
*

*> > deserve more thought that we sometimes give them.
*

*> >
*

*> > I would like to see some postings on bypass capacitor criteria that
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*> > people use in everyday work.
*

*> >
*

*> > Here is a quick way of measuring ESR, capacitance, and inductance of a
*

*> > capacitor. Connect a 5 V logic pulse generator through 100 Ohms to the
*

*> > resistor. Keep all leads shorter than 1/2 cm. I do this by putting a
*

*> > 100 Ohm carbon comp 1/2 watt resistor into a BNC female jack with one
*

*> > lead clipped so the body fully inserts into the jack. I then solder the
*

*> > capacitor to the exposed end of the resistor whose lead is clipped to a
*

*> > stub. The other end of the cap solders to the BNC shell. The generator
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*> > should have a 1 to 2 ns risetime. Give the capacitor one pulse while
*

*> > looking at the first few tens of mv of the exponential rise. You will
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*> > see a peak, an offset, and an upward slope. The peak is from e =
*

*> > L*di/dt, the offset from ESR, and the slope from the capacitance. It is
*

*> > pretty easy to calculate these parameters from the scope screen. Probe
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*> > quality is very important so do not use one with a capacitive input
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*> > impedance, a probe built from a 1000 Ohm resistor and a piece of coax
*

*> > will work well.
*

*> >
*

*> > Here is my attempt at an ASCII diagram of the scope waveform:
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*> >
*

*> > -- slope gives capacitance from i = c*dv/dt
*

*> > --
*

*> > / -- --------
*

*> > / \ -- e=Ldi*dt
*

*> > / \ --
*

*> > / -- ----- --------
*

*> > -------/ ----- ESR
*

*> >
*

*> > When paralleling capacitors (large and small ones for greater
*

*> > bandwidth), this method will alert you if the small one is resonating
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*> > with the inductance of the large one.
*

*> >
*

*> >
*

*> >
*

*> > Doug
*

*> >
*

*> > Larry Smith wrote:
*

*> >
*

*> > > Andrew Phillips wrote:
*

*> > > > I would be interested to hear other people's favourite 'Screwy SI
*

*> > > > Concept' - why its screwy and why you think it has hung around in the
*

*> > > > literature confusing everybody.
*

*> > >
*

*> > > I nominate "Extremely low series resistance is important in a bypass
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*> > > capacitor."
*

*> > >
*

*> > > Once you launch a transient into a power distribution system, it
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*> > > has to be dissipated by something. A little series resistance
*

*> > > can be a good thing.
*

*> >
*

*> > Whooaa... I'll take issue with that one. If you give me a set of high
*

*> > frequency X7R and NPO ceramic capacitors with half of the ESR, I will
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*> > build you a power distribution system with half of the number of
*

*> > decoupling capacitors. The number of capacitors required is inversly
*

*> > proportional to the ESR.
*

*> >
*

*> > One of our typical products might have 200 decoupling capacitors on one
*

*> > power rail in order to provide clean transient power up to several
*

*> > hundred MHz to 70 watt processors. I can cut that number to 100 if I
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*> > have capacitors with half the ESR. That saves precious board area,
*

*> > wiring congestion and cost.
*

*> >
*

*> > Sorry, I cannot second that nomination. In fact, I am doing everything
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*> > I can to convince capacitor vendors to offer low ESR ceramic
*

*> > capcitors.
*

-- D. C. Sessions [email protected]**** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

**Next message:**Douglas McKean: "Re: [SI-LIST] : What's your favorite Screwy SI Concept?"**Previous message:**Hank Zauderer: "[SI-LIST] : Update on SI manager position..."**In reply to:**Larry Smith: "[SI-LIST] : low ESR decoupling capacitors"**Next in thread:**Larry Smith: "Re: [SI-LIST] : low ESR decoupling capacitors"

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