RE: [SI-LIST] : PLL clock buffer chips and the feedback loop

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From: Andy Peters (apeters@noao.edu)
Date: Thu Apr 06 2000 - 14:58:35 PDT


Stephen,

> I've been following this thread off and on, mostly becasuse I'm involved
> doing the same exact type of design -- distributing clocks to an FPGA and
> banks of SRAM using RoboClock. If your clock driver is short of outputs,
> and your FPGA is from the Xilinx Virtex family, one option is to drive the
> SRAMS clocks from the FPGA using a DLL clock mirror. The technique is
> described in the Xilinx app notes. Depending on the number of outputs
> required, I've acheived 350ps of skew between the clock at the FPGA input
> and the clock(s) at the SRAMS.

Nope, it's a 4KXLA part. I didn't want to deal with a 2.5v power supply (in
addition to the 3.3V and the 5V). Another concern was that when I started
this project, there were still issues with the Xilinx tools and the Virtex
parts.

Had I started this project today, I would have used a Spartan2 part and a
different VME interface chip set. But, you know, you rolls your dice and
you moves your mice . . .

best,

a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520 318 8191
apeters@noao.edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens

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