Re: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs

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From: Vinu Arumugham (vinu@cisco.com)
Date: Fri Feb 11 2000 - 10:12:18 PST


Netzler Dirk wrote:

> Hello All,
>
> every time I have to design memory buses I wonder wether signals at adress
> inputs
> of synchronous memory chips (SDRAM, SSRAM) ) must have monotonic edges or
> not.
> If yes, can anybody give me an explanation for that ?
>
> And what's about FEPROMs ? Okay, the control signals (e.g. WE,OE) need to be
> monotonic.
> But what's about the adress inputs ? Should they be monotonic, too ? I don't
> find reasons for that.
>

On asynchronous parts, an address change can cause a write whenWE is asserted. Address non-monotonicity can therefore cause a failure.

>
> What are your experiences ?
>
> Best regards
>
> Dirk Netzler
> Siemens AG
>
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