Re: [SI-LIST] : meaning and value of C_comp

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From: D. C. Sessions (dc.sessions@vlsi.com)
Date: Wed Mar 22 2000 - 09:57:41 PST


Mike LaBonte wrote:
>
> D.C., isn't Greg describing a reason why C_comp measured at 1MHz
> can be larger than the effective C_Comp seen at "real" speeds?

Depends. The errects (or contributors, if you will) he describes
are real (or complex ;-) ) and some of them only kick in at really
high frequencies. Others become negligible at 'frequencies of interest.'

My point is that a fairly simple C_comp model works Well Enough For
Government Work if it matches the effective response for steps on
the order of 300 ps edge time.

> "D. C. Sessions" wrote:
> >
> > gedlund@us.ibm.com wrote:
> > >
> > > Here's another thing to consider: what if you have an on-chip series
> > > resistor? Physically speaking, some of the C_comp is distributed on the
> > > FET side of the resistor, and some of it is on the pad side. Behavioral
> > > simulators assume that all C_comp is in once place and all of the impedance
> > > is in one place (from a network topology point of view). When the device
> > > is tri-stated you still have a distributed network in real life, but you
> > > have a very high impedance plus a lumped capacitance in your behavioral
> > > model. This almost begs for a distributed model.
> > >
> > > I like to use a TDR to measure pin capacitance in the lab, but I'm not even
> > > sure that a TDR will give you the right answer in this case.
> >
> > The good news is that it doesn't matter.
> > Even the dominant effect of C_comp is down in the ~50 ps ballpark; the
> > second- and third-order contributors are truly in the noise.
> >
> > > ---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
> > > 03/21/2000 04:06 PM ---------------------------
> > >
> > > "D. C. Sessions" <dc.sessions@vlsi.com> on 03/21/2000 02:53:40 PM
> > >
> > > To: si-list@silab.eng.sun.com
> > > cc: ibis-users@eda.org
> > > Subject: Re: [SI-LIST] : meaning and value of C_comp
> > >
> > > Weston Beal wrote:
> > > >
> > > > Dear IC experts,
> > > >
> > > > I've been working a problem that might involve the C_comp parameter in an
> > > > IBIS file. In discussion with others, I find some difference of opinion.
> > > > the IBIS spec says that C_comp represents the capacitance on the die. I
> > > > understand this to be the bond pad, clamp diode reverse bias capacitance,
> > > > and final stage transistor channel capacitance. What other effects are
> > > > important contributors to C_comp? I suspect that the bond pad is the
> > > > dominant factor in todays technology. Is that correct? What are typical
> > > > values for the components I've listed?
> > >
> > > C_Comp is whatever value most closely approximates the high-frequency
> > > response that an incoming wave 'sees' hitting the IC. Personally, I
> > > prefer deriving it from doing a best-fit optimization matching a cap
> > > to a fully extracted SPICE netlist of the physical part. For most
> > > I/O cells this runs just a bit over 1.0 pf, mostly in the gate/drain
> > > capacitance of the output devices. The other contributors (diffusion
> > > to bulk, pad to substrate) have such high ESR as to be negligible.
> > >
> > > Warning: most test groups want to measure input capacitance at 1 MHz,
> > > and this gives dramatically higher values. There's been blood on the
> > > floor in JEDEC meetings over this very difference.
> > >
> > > --
> > > D. C. Sessions
> > > dc.sessions@vlsi.com
> >
> > --
> > D. C. Sessions
> > dc.sessions@vlsi.com
>
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-- 
D. C. Sessions
dc.sessions@vlsi.com

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