RE: [SI-LIST] : LVDS questions

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From: Degerstrom, Michael J. (degerstrom.michael@mayo.edu)
Date: Wed Feb 02 2000 - 12:44:52 PST


I have a few opinions which hopefully will be of value.

WRT LVDS, I think that if a circuit is used to switch (reverse)
about 3.5ma in different directions through a 100 ohm
resistor while maintaining about 1.2V common mode voltage across
this 100 ohm resistor then one could call this circuit a valid LVDS
output buffer. As long as the differential transmission line
impedance matches the 100 ohm termination, then it shouldn't
be too critical whether the output nodes look like high, low,
or impedance match the transmission lines. Also, the pushing
and pulling nodes can be of different impedances. The important
criteria is how smoothly the push-pull design transitions states.
I can see where it may be important for matching pushing and pulling
impedances if your transmission line impedance does not match closely
to the 100 ohm termination resistor. I would like to investigate
this scenario when I have more time.

The power used by LVDS is simply 3.5ma x VDD.

Open collector CML switches a constant current from one 50 ohm
terminated line to another. Thus the BIG difference
between CML and LVDS is that since CML does not reverse
the current through the termination resistor as is done with
LVDS. Therefore CML consumes twice the power for the same current
draw and power supply value as that used for LVDS.

CML is often "back-terminated" with 50 ohm resistors between
VCCO and the collectors. This arrangement allows for
50 ohm source impedance and if far-end terminated with 50 ohms
to VCCO then 4 times the power is consumed for the same signal
swing and power supply as that used for LVDS.
 
ECL or PECL sources 22ma in HIGH state and 6ma in LOW state
to a supply 2 volts lower than the power supply. Therefore,
each t/c pair consumes 56 mW. Compare this to LVDS for
a 3.3V supply which consumes about 12mW per t/c pair and
8ma CML with a -4.5V supply consuming 36mW per t/c pair, then
one can see why CML is so attractive.

Mike
_______________________________________________________________
Mike Degerstrom Email: degerstrom.michael@mayo.edu
Mayo Clinic
200 1st Street SW
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Rochester, MN 55905 FAX: (507) 284-9171
WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html
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> -----Original Message-----
> From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
> Sent: Tuesday, February 01, 2000 2:39 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : LVDS questions
>
>
> Tom Zimmerman wrote:
>
> > 1. My basic understanding of LVDS (which may be incorrect)
> is that a
> > constant current of several mA is supplied to one of the
> output pads (pads
> > are terminated in approx. 100 ohms) in order to supply a voltage
> > differential across the load of several hundred mv. In
> order to establish a
> > common mode voltage (approx. 1.2 V), the other pad must
> effectively be
> > connected to a voltage source. Is this really the way
> LVDS is done?
>
> No. LVDS requires that the difference between Vos (output
> common mode) and
> Vod (output differential) for one and zero be kept pretty
> small. In other
> words, signaling must be balanced.
>
> >
> This
> > configuration seems inherently unbalanced, since one output
> pad is low
> > impedance, the other high impedance. It seems that this
> would reduce common
> > mode noise rejection. Wouldn't a balanced configuration be
> more desirable??
>
> Indeed, and that's why it is. Oh, and the Rs is also constrained.
>
> > 2. How does LVDS compare to other schemes such as PECL or
> CML (is CML just
> > essentially 2 open collectors which switch a current to one
> output pad or
> > the other??). Is there some consensus as to a superior
> scheme, or does each
> > scheme have its own advantages and disadvantages depending on the
> > application?
>
> CML has the extremely nice properties of
>
> 1) really, really, low differential skew (it's easy to
> balance the drive)
> 2) simple receiver (the common-mode issue is easy for current drive)
>
> and the truly ugly property of
>
> 3) hideous power dissipation.
>
> PECL, on the other hand, has nasty habits of its own. My
> unfavorite is
> its reference to the positive rail, which is naturally the
> one that keeps
> moving as supplies migrate downward.
>
> Bothe LVDS and PECL, being push/pull, have problems with
> crossover noise.
> Both have the additional nasty of common-mode points offset
> from EITHER
> supply, which makes doing them in advanced (read low-voltage)
> processes
> ugly to impossible.
>
> > 3. Some time ago I was asked to provide low-level
> differential LVDS-like
> > digital outputs on a chip I designed. I ended up
> > simply switching the output pads between 2 equal valued
> on-chip resistors
> > (hundreds of ohms), one connected to ground, the other to a
> positive low
> > impedance voltage source. In other words, this scheme is
> like LVDS except
> > it uses 2 equal valued current sources of rather low output
> impedance (the
> > resistors). The common mode output voltage then lies at
> half the positive
> > voltage source value. I was attracted to this scheme
> (perhaps naively)
> > because of its inherent simplicity and its balanced nature.
> The users of
> > this chip report that it works just fine and that they are
> pleased with the
> > performance. I would like to know what the disadvantages
> of this approach
> > might be (since I am considering using it again). Is this
> a silly thing to
> > do, and if so, why? Isn't a balanced output preferable to
> unbalanced
> > (if LVDS is indeed unbalanced)?
>
> I've seen LVDS drivers done this way. Assuming that you can
> get the common-mode
> point into the rather narrow allowed range I don't know of
> any reason why it
> shouldn't work.
>
> --
> D. C. Sessions
> dc.sessions@vlsi.com
>
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