RE: [SI-LIST] : SSC

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From: Zhang, Michael T (michael.t.zhang@intel.com)
Date: Tue Mar 14 2000 - 09:29:57 PST


Ravinder,

As you said, SSC is a percentage frequency modulation. So it spreads the
higher harmonic of clock frequency over a wider MHz range, therefore, brings
a larger amount of EMI reduction of the peak amplitude, NOT higher emission.
This has been seen in actual PC systems. In addition, SSC benefit increases
at frequencies over 1GHz due to the use of average detector.

SSC itself does not introduce more jitter because of the small percentage of
frequency modulation. This is the reason it has been successfully used with
RDRAM, which has 400MHz differential clocks with very tight jitter
requirement. However, SSC can not be used on any fixed frequency clocks,
like USB.

-Michael T. Zhang
Processor Product Development
Performance Microprocessor Division, Intel Corp.
(503) 264-2301

-----Original Message-----
From: ajmani@us.ibm.com [mailto:ajmani@us.ibm.com]
Sent: Tuesday, March 14, 2000 8:37 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : SSC

It is a common misconception that Spread Spectrum clocks lower the
emissions. Actually, they just spread the emission in to a larger
frequency band. Since the measurement bandwidth for EMI receivers is 120
kHz, the measured value of emissions goes down. It is a perfectly legal
way of cheating the compliance agencies, and present day high-speed PC
motherboards often use these clocks. However, applications requiring low
jitter clock (e.g. serial communication applications) can't use this type
of clock. Also, because the frequency spread is a percentage of clock
frequency, you may see broad band noise at higher harmonics of the clock.
Thus, it is possible for the emissions to go up at the higher frequency
bands.

Regards,
Ravinder Ajmani
PCB Development and Design Department
IBM Corporation - Storage Systems Division
Email: ajmani@us.ibm.com
***************************************************************************
Always do right. This will gratify some people and astonish the rest.
.... Mark Twain

sweir <weirsp@a.crl.com>@silab.eng.sun.com on 03/13/2000 11:55:11 PM

Please respond to si-list@silab.eng.sun.com

Sent by: owner-si-list@silab.eng.sun.com

To: si-list@silab.eng.sun.com
cc:
Subject: Re: [SI-LIST] : SSC

SSC synthesizers modulate the clock output frequency at a fairly low rate
in order to spread the frequency spectra of the clock. Since the EMI
energy that is constant is now spread over a wider band, the peak level
falls. This can buy several db improvement.

The PLL must stably track the bandwidth of the SSC clock source without
gaining or losing more phase than allowed for in the timing budget. Be
careful if the PLL uses a phase-frequency detector, as these devices have a
gain dead-band at zero error that causes phase jitter. A typical fix is to
bias the error amplifier with a little DC, so that they do not quite get to
zero error. However, when you use an SSC, the loop gets pushed around a
little, and depending on the coefficients could push the part back into the
deadband.

ICS( Cypress ) among others build these things.

Regards,

Steve.
At 03:09 PM 3/14/00 +0800, you wrote:
>Dear Gurus,
>
>What is a Spread Spectrum Clock synthesizer and why it is used in PC
>motherboards? What are the limitations when chosing a PLL for the
Registered
>DIMM if you need to support SSC? Do you know of any such chips?
>
>With best regards,
>Subas Bastola
>
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