Re: [SI-LIST] : LVDS driving PCML

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From: Raymond.Leung@qsa.idt.com
Date: Wed Mar 08 2000 - 20:44:08 PST


Julia,

One thing coming up my mind is whether you have simulated the
receiver with all the corner models which reflecting all the possible
combination of changes of parameter values due to process variations.
The other thing is how 'real' is your receiver spice netlist compared
to the chip company's in-house netlist.

As you have mentioned about the simple termination theme with
which a 100 ohm resistor is placed across the the T-lines, I would
wonder the control of the common mode fluctuations which would
lead to received data edge jitter due to the limited CMRR bandwidth
at the receiver.

Raymond

Julia Nekrylova <julian@cyras.com> on 09/03/2000 12:41:26

Please respond to si-list@silab.eng.sun.com

To: "'si-list@silab.eng.sun.com'" <si-list@silab.eng.sun.com>
cc: (bcc: Raymond Leung/QSA/AU)

Subject: [SI-LIST] : LVDS driving PCML

Dear SI-LIST,

My question is about LVDS logic with Voh = 1.4V and Vol = 1.0V
driving the PCML receiver. The problem is that the common mode voltage
input range of the PCML receiver should not be less than 1.3 V (and not more
than 2.0V).
I really would like to terminate the differential transmission line with 100
Ohm line-to-line resistor only.
In that case I am out of the PCML common mode input range by 0.1 V.
We HSPICEd this circuit and the simulator showed that even the common mode
input voltage of 0.8 V would not be a problem.

So, my question is, are there any hidden problems (reliability etc.) with
this
differential driver-receiver logic selection that
I am not aware of?

Thank you in advance,
Julia Nekrylova

Cyras Systems, Inc.

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