[SI-LIST] : PWR/GND grid effect on EMI

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From: Ilya Zaverukha (engr@servtech.com)
Date: Tue Apr 04 2000 - 19:00:39 PDT


Hello SI experts,

I'm relaying out a pcb for one of my customers. The goal is to reduce the cost
by going from 4-layer (internal PWR and GND planes) bd. down to 2-layers. One
of the major concerns is increased EMI.
One of the ideas that was brought up to minimize EMI is to have a "grid" of
horizontal PWR traces spaced around 2cm from each other on top side and
vertical GND traces spaced 2cm on the opposite side. In addition, the board
would have a GND ring around the perimeter on both sides that would be stiched
with vias. Every point of intersection of these PWR and GND lines will have a
.01uF and .1uF bypass cap.
Since I haven't heard about this approach, your input would be appreciated.

Thanks,
--Ilya Z.
IZ Circuits

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