[SI-LIST] : on-chip decoupling capacitance

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From: [email protected]
Date: Wed Apr 12 2000 - 13:26:00 PDT

There has been a lot of good discussion on this list about decoupling capacitance for high
performance systems. So far, I believe, all of this discussion has been around the
quantity and quality of capacitors mounted on the substrate. My question is in regards to
whether this is adequate for very high speed, low voltage core logic in deep sub-micron
Are we at a point where the external capacitors are so far away from the core logic (i.e.,
separated by bond wires and IC power grid routing) that something more is needed on-chip?
(In addition to, not in place of the board caps.)
I have heard rumors that modern microprocessors use 10s of nF of on-chip decoupling
(presumably provided by large areas of thin oxide) to keep the core supply noise in a
range where the flip-flops don't loose their minds.
Can anyone on this list point me to published resources that discuss this issue and when
I'm going to get myself into trouble? Is this a problem only for ICs using dynamic logic
which may be more noise sensitive? I'm doing my first 0.25 um design and I'm beginning to
understand some of the on-chip SI issues, but this is one I haven't heard much about.

Does anyone know of a similar email reflector that deals with chip design issues such as
this, or are we SI guys the only ones lucky enough to have a Ray Anderson to set something
like this up?

Chris Simon
Electrical Engineer
General Dynamics Information Systems

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