From: Stuart Adams (firstname.lastname@example.org)
Date: Thu Mar 23 2000 - 14:08:38 PST
> Hi Stuart,
> You don't specify the signalling system going thru the connector.
Well, in my case the signaling system is all 3.3 volt CMOS (with
5 volt PCI compliance). The connector is 160 pins and contains
an embedded PCI bus (at 33 MHz), 16 pins of video data, 10/100 ethernet
and various slower discrete I/O.
I currently have 20 pins allocated for GNDs, spread throughout the
connecter (more less the same as the PCI spec). In most cases the
board will run from a 3.3v LDO linear regulator on the board and I
have 3 pins allocated for unregulated DC in. In some cases the
board will operate from externally supplied 3.3 volts and I
have 3 pins allocated for external VCC. (Worst case steady state
current is only 600 mA - max current spec'd per pin for the
connector is 500 mA)
Our board is 1.4" x 2.4" and has about 40 bypass caps and four 47uF
bulk tantalums. Our customer's will designing the motherboard it mates
to so we can't predict what it will look like for simulation but we could
provide them some design guidelines for bypassing/layout.
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