RE: [SI-LIST] : monotonic signals at SDRAM-, SSRAM- and FEPROM-a dress inputs

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From: Peterson, James F (FL51) (james.f.peterson@honeywell.com)
Date: Mon Feb 14 2000 - 08:11:03 PST


Regarding non-monotonic edges on SDRAM :
I have also heard that SDRAMs are very sensitive to this problem. I don't
think the responses so far have completely explained why a non-monotonic
edge on an address line can cause a problem in synchronous memory.
Does anyone have a good explanation for why this occurs?
thanks,
Jim
Jim Peterson
jfpeterson@space.honeywell.com
Honeywell, Space Systems Division, M/S 934-5
13350 US 19 N., Clearwater, FL, 34624
727-539-2719

-----Original Message-----
From: Netzler Dirk [mailto:Dirk.Netzler@icn.siemens.de]
Sent: Friday, February 11, 2000 2:02 AM
To: 'si-list@silab.eng.sun.com'
Subject: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and
FEPROM-adress inputs

Hello All,

every time I have to design memory buses I wonder wether signals at adress
inputs
of synchronous memory chips (SDRAM, SSRAM) ) must have monotonic edges or
not.
If yes, can anybody give me an explanation for that ?

And what's about FEPROMs ? Okay, the control signals (e.g. WE,OE) need to be
monotonic.
But what's about the adress inputs ? Should they be monotonic, too ? I don't
find reasons for that.

What are your experiences ?

Best regards

Dirk Netzler
Siemens AG

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