From: D. C. Sessions (firstname.lastname@example.org)
Date: Thu Mar 02 2000 - 13:45:15 PST
Vinu Arumugham wrote:
> Scott McMorrow wrote:
> > One could argue that isolating only the Vcc pin for an analog
> > device, without also isolating the ground pin through ferrites
> > only isolates the device from half of the possible noise. Since
> > ground still wiggles, there will be noise on the PLL Vcc pin
> > relative to ground. Isolation using two ferrites would provide
> > higher noise isolation.
> If the on-chip PLL GND and VCC structures are symmetric,
> I think using two ferrites, one each on the VCC and GND pins will
> be no different from using two ferrites in series only on the PLL VCC
> pin and connecting PLL GND directly to digital GND.
Alas, the on-chip Vcc and Vss structures are far from symmetrical.
Triple-well structures are quite rare, so the majority of ICs use
P- substrates with N- wells for the P-channel transistors. The result
is that all of the N-channel devices are exposed to bulk silicon
potentials and the bulk material needs to be tied to ground. This
results in all sorts of interesting currents in the substrate.
Partly because of this, low-noise circuitry in mixed-signal CMOS
tends to use P-channel transistors for the most critical devices.
It also means that the positive PLL supply will have very little
noise injected onto it, and the negative supply will have a LOT
of noise potential.
A final complication is that the PLL eventually has to drive external
circuitry on the digital ground domain. Don't forget the signal
> > However, one must be sure to provide
> > adequate isolation from other parasitics where noise
> > could be coupled into the circuit, such as nearby signal lines,
> > coupled pins in the package, large planes or fill areas where
> > there could be additional capacitive coupling parasitics ... etc.
> > regards,
> > scott
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR 97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> > Chris Bobek wrote:
> > > Hi,
> > >
> > > I came across a schematic that shows the PLL ground of an IC connected
> > > to ground through an inductor. The Vcc pin of the device is connected
> > > to a bunch of caps and an inductor to Vcc.
> > >
> > > I understand and have used an inductor (or a resistor) with a bunch of
> > > decoupling caps on Vcc for applications like this. But, I've always
> > > tied the Gnd pin(s) directly to ground. It doesn't make any sense to me
> > > why you would want to add inductance in the path of any ground. It
> > > seems you would just add switching noise to your device.
> > >
> > > Can somebody explain whether this is common practice, or whether it was
> > > a poor design (sorry I don't have more information on the particular
> > > device).
-- D. C. Sessions email@example.com
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