**From:** Mike Jenkins (*[email protected]*)

**Date:** Mon Apr 17 2000 - 14:26:26 PDT

**Next message:**S. Weir: "RE: [SI-LIST] : AC Coupling vs DC Coupling"**Previous message:**Bradley S Henson: "[SI-LIST] : HSPICE Vector File Problem"**In reply to:**Greim, Michael: "[SI-LIST] : Question on propagation delay........"

Michael,

Here's my two cents. By 'different widths' I assume you

mean the PCB cross section is the same. Hence, the

characteristic impedance is different for the three nets.

This would probably have profound effects on the driver

delay.

Second, if the nets are routed on internal planes, then

the propagation velocity would indeed depend only on the

dielectric. But, for external planes, wider traces would

put more of the field into the board and less in the air,

slowing the propagation.

Third, the effect of a via depends on where the return

current flows. If (as many contributors have previously

described) the change in signal layers involves a change

in current return layers, then the current return has to

find a path. If it's a significant detour, that looks

inductive, adding delay. A high frequency decap between

the two planes and near to the via minimizes this effect.

Regards,

Mike

"Greim, Michael" wrote:

*>
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*> Hi everyone,
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*>
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*> Here is what I thought was a simple question but
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*> has turned into a discussion of some debate. Three
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*> nets are routed on a pwb as stripline structure. They
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*> are driven by the same type of driver and have the same
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*> type of receiver. There is one driver and one receiver per
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*> net. They contain the same number of vias in the same
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*> location on the nets with the same padstack. The only
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*> topological difference of the nets is that they are routed
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*> as different widths. That being said, what is the flight
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*> time of these topologies as a function of length. Is it
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*> strictly a function of the dielectric? What is the relative
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*> effect of varying number (say difference of no more than
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*> a handful) of vias on the nets.
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*>
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*> Whaddya think?
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*> >
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Mike Jenkins Phone: 408.433.7901 _____ LSI Logic Corp, ms/G715 Fax: 408.433.7461 LSI|LOGIC| (R) 1525 McCarthy Blvd. mailto:[email protected] | | Milpitas, CA 95035 http://www.lsilogic.com |_____| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****

**Next message:**S. Weir: "RE: [SI-LIST] : AC Coupling vs DC Coupling"**Previous message:**Bradley S Henson: "[SI-LIST] : HSPICE Vector File Problem"**In reply to:**Greim, Michael: "[SI-LIST] : Question on propagation delay........"

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