From: Jon Keeble (firstname.lastname@example.org)
Date: Fri Mar 31 2000 - 18:40:23 PST
Following advise from this list, for 10 layer boards I prefer the following
LAYER1 TOP LAYER (CONDUCTOR)
LAYER10 BOTTOM LAYER (CONDUCTOR)
This puts the power planes close together (maxim distributed capacitance)
and close to the surface (minimum impedance between silicon and power
I used to think that it was useful to minimise the inductance between the
bypass caps and the power planes. However, each capacitor has a low
impedance over a range of frequencies centered on its self resonance, and an
extra nH or two simply moves this range down. Recent work revealed in this
list shows that a number of different, close-spaced values can deliver a low
impedance over the full spectrum.
I don't think it matters which way round VCC and GND goes.
The middle routing layers can be routed at 0, 30,60,90 degrees to minimise
>From: Sunil Kumar <email@example.com>
>To: firstname.lastname@example.org <email@example.com>
>Date: Saturday, April 01, 2000 11:25 AM
>Subject: [SI-LIST] : via capacitance
>>Dear all SI experts.
>>I am using a multilayer board having the following stack-up:
>>LAYER1 TOP LAYER (CONDUCTOR)
>>LAYER10 BOTTOM LAYER (CONDUCTOR)
>>A signal trace is going from layer7 to layer8. A through-hole via is
>>The via is having pads on layers 1,7,8,10. There are antipads on the
>>planes. Is there any formula/tools to calculate the exact capacitance of
>>the via?? How can I measure it in the board??
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