Re: [SI-LIST] : on-chip decoupling capacitance (and SI)

About this list Date view Thread view Subject view Author view

From: D. C. Sessions ([email protected])
Date: Wed Apr 19 2000 - 10:55:51 PDT


"Zabinski, Patrick J." wrote:
>
>
> > Case in point: we just ran the onchip capacitance extraction
> > for a customer
> > device. 200nm technology, before adding intentional bypass
> > devices, the
> > assorted sources of supply capacitance came to ~230 nF in the
> > 100-1000 MHz
> > range.
>
> D.C.
>
> Can you shed some light as to what you mean by "assorted
> sources of supply capacitance"? It's hard for me to believe
> 230 nF of trace/grid-capacitance, so I'm struggling to figure
> out where it's coming from.

Most of your logic is quiescent. RAMs especially. And when
you get down to it, that means that you have a great deal
of gate-source capacitance in series with fully-on source-drain
paths. The net effect is a truly enormous amount of charge
reservoir, damped by parallel high-ESR drain-well and
well-substrate capacitance.

-- 
D. C. Sessions
[email protected]

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:14 PDT