Re: [SI-LIST] : on-chip decoupling capacitance (and SI)

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From: D. C. Sessions (
Date: Wed Apr 19 2000 - 10:55:51 PDT

"Zabinski, Patrick J." wrote:
> > Case in point: we just ran the onchip capacitance extraction
> > for a customer
> > device. 200nm technology, before adding intentional bypass
> > devices, the
> > assorted sources of supply capacitance came to ~230 nF in the
> > 100-1000 MHz
> > range.
> D.C.
> Can you shed some light as to what you mean by "assorted
> sources of supply capacitance"? It's hard for me to believe
> 230 nF of trace/grid-capacitance, so I'm struggling to figure
> out where it's coming from.

Most of your logic is quiescent. RAMs especially. And when
you get down to it, that means that you have a great deal
of gate-source capacitance in series with fully-on source-drain
paths. The net effect is a truly enormous amount of charge
reservoir, damped by parallel high-ESR drain-well and
well-substrate capacitance.

D. C. Sessions

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