**From:** Larry Smith (*[email protected]*)

**Date:** Fri Mar 17 2000 - 10:17:04 PST

**Next message:**[email protected]: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Previous message:**Muranyi, Arpad: "RE: [SI-LIST] : Bad IBIS models!"**Maybe in reply to:**mjs: "[SI-LIST] : Fast edges with limited plane capacitance"**Next in thread:**Vinu Arumugham: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**Vinu Arumugham: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**Ron Miller: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**Paul Thompson: "Re: [SI-LIST] : Fast edges with limited plane capacitance"

This is an excellent place to apply the "basic question" principles

from today's other thread on SI-list. Given a pair of power planes

in FR4 material (eR=4), we know that the velocity of propagation

is light_speed/sqrt(4) = 1.5x10**8 M/sec = vel.

The capacitance is simply Ca = eR/thk where Ca is capacitance per

area (Farads/M**2) and thk is the thickness of the dielectric.

The inductance the power planes is calculated from vel = sqrt(La/Ca)

where La is the spreading inductance (Henries per square of

material, just like spreading resistance in a sheet of material).

The impedance is Zl = sqrt(La/Ca). The units Zl for power planes

come out in Ohm-M. This is interpreted as the impedance for a

plane wave propagating down a strip of this material that is 1

meter wide. Divide by the actual width to get the actual impedance

in Ohms.

Note that we have a homogenous environment between the two power

planes. Things get a little more complicated if we have an

non homogenous environment (ie both FR4 and air dielectrics involved).

So, if we compare the two power plane pairs below with 4 and 40 mil

separations:

The velocities are constant.

The capacitance of the 4 mil planes is 10X the 40 mil plane.

The inductance of the 40 mil plane is 10X the 4 mil plane.

The impedance of the 40 mil plane is 10X the 4 mil plane.

To directly answer Mark's questions, with the same amount of noise

stimulation, there will be much more noise between the 40 mil power

planes than between the 4 mil planes, in fact 10X. The reason is

because of the increased impedance.

It turns out that one of the most important consequences of thin power

planes is the 10X decrease in inductance. This greatly increases the

effectiveness of the discrete decoupling capacitors that are mounted on

the power planes.

I vote for the s-s-G-P-s-s stackup. Not only does it have better

capacitance properties, but it also has better inductance and impedance

properties. SI and EMI noise are greatly reduced. Microstrip

transmission lines work just fine.

regards,

Larry Smith,

Sun Microsystems

*> Date: Fri, 17 Mar 2000 10:29:33 -0600 (CST)
*

*> From: mjs <[email protected]>
*

*> To: "'[email protected]'" <[email protected]>
*

*> Subject: [SI-LIST] : Fast edges with limited plane capacitance
*

*> MIME-Version: 1.0
*

*>
*

*>
*

*> Let's assume that a power subsystem has a low, flat impedance up to a few
*

*> hundred MHz, and has a pair of realtivly unbroken planes. Only problem is
*

*> that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
*

*> will be a problem unless all noisy digital signals are 'sandwiched'
*

*> between the planes. This board also has parts with 1-2ns edge rates.
*

*>
*

*> I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
*

*> allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
*

*> yielding much greater plane capacitance.
*

*>
*

*> My questions is this: How does a lack of planar capacitance contribute
*

*> to increasing EMI? It seems that not having the proper plane capacitance
*

*> would tend to slow edge rates and possibly be one of the lesser SI sins.
*

*>
*

*> Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
*

*> decreasing EMI?
*

*>
*

*> Regards,
*

*> Matt Stanik
*

*> PCB Design Engineer
*

*>
*

*>
*

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**Next message:**[email protected]: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Previous message:**Muranyi, Arpad: "RE: [SI-LIST] : Bad IBIS models!"**Maybe in reply to:**mjs: "[SI-LIST] : Fast edges with limited plane capacitance"**Next in thread:**Vinu Arumugham: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**Vinu Arumugham: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**Ron Miller: "Re: [SI-LIST] : Fast edges with limited plane capacitance"**Reply:**Paul Thompson: "Re: [SI-LIST] : Fast edges with limited plane capacitance"

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