Re: [SI-LIST] : Input switching threshold & CPCI

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From: Adrian Shiner (adrian.shiner@virgin.net)
Date: Tue Jan 04 2000 - 11:23:24 PST


Size does not necessarily mean that you have the best thoughts..dinosaurs
were pretty big but where are they now?

Adrian
----- Original Message -----
From: D. C. Sessions <dc.sessions@vlsi.com>
To: <si-list@silab.eng.sun.com>
Sent: 04 January 2000 17:44
Subject: Re: [SI-LIST] : Input switching threshold & CPCI

> Abe Riazi wrote:
> >
> > D. C. Sessions Wrote:
> > >
> > >PCI does the old (idiotic) 0.8-2.0 input thresholds that were first
> > >documented on cave walls. In contrast, anyone trying to do serious
> > >signaling at nontrivial speeds uses very tight thresholds, usually
> > >scaled to the driver supply and usually with differential receivers.
> > >
> > Hi D. C.,
> >
> > This is a good point. For 3.3 V signaling, the input voltage threshold
> > values (based on PCI specs) consist of:
> >
> > Minimum Vih (Input High Voltage) = 0.5 Vcc
> > Maximum Vil (Input Low Voltage) = 0.3 Vcc
>
> Hmmm... 0.9v to 1.8v -- slightly tightened TTL again.
> The big evil of course is the 0.4 Vcc centerpoint, which
> Intel reflects in their drive specs making for rotten
> line matching. They made the same mistake with AGP
> (Vref of 0.39 to 0.41 Vcc, 2/3 PCI drive) even though
> there wasn't any need for backward compatibility.
>
> At least it's scaled. I'm tired of arguing with customers
> who insist on running timing analyses against Vih(max) at
> slow corner Vcc min.
>
> --
> D. C. Sessions
> dc.sessions@vlsi.com
>
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